linux-kernel - Re: [v3,11/41] mips: reuse asm-generic/barrier.h

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Message-ID: <56994068.4050402@imgtec.com>
Date:	Fri, 15 Jan 2016 10:54:32 -0800
From:	Leonid Yegoshin <Leonid.Yegoshin@...tec.com>
To:	Will Deacon <will.deacon@....com>,
	"Paul E. McKenney" <paulmck@...ux.vnet.ibm.com>
CC:	Peter Zijlstra <peterz@...radead.org>,
	"Michael S. Tsirkin" <mst@...hat.com>,
	<linux-kernel@...r.kernel.org>, Arnd Bergmann <arnd@...db.de>,
	<linux-arch@...r.kernel.org>,
	Andrew Cooper <andrew.cooper3@...rix.com>,
	Russell King - ARM Linux <linux@....linux.org.uk>,
	<virtualization@...ts.linux-foundation.org>,
	Stefano Stabellini <stefano.stabellini@...citrix.com>,
	Thomas Gleixner <tglx@...utronix.de>,
	Ingo Molnar <mingo@...e.hu>, "H. Peter Anvin" <hpa@...or.com>,
	Joe Perches <joe@...ches.com>,
	David Miller <davem@...emloft.net>,
	<linux-ia64@...r.kernel.org>, <linuxppc-dev@...ts.ozlabs.org>,
	<linux-s390@...r.kernel.org>, <sparclinux@...r.kernel.org>,
	<linux-arm-kernel@...ts.infradead.org>,
	<linux-metag@...r.kernel.org>, <linux-mips@...ux-mips.org>,
	<x86@...nel.org>, <user-mode-linux-devel@...ts.sourceforge.net>,
	<adi-buildroot-devel@...ts.sourceforge.net>,
	<linux-sh@...r.kernel.org>, <linux-xtensa@...ux-xtensa.org>,
	<xen-devel@...ts.xenproject.org>,
	"Ralf Baechle" <ralf@...ux-mips.org>,
	Ingo Molnar <mingo@...nel.org>, <ddaney.cavm@...il.com>,
	<james.hogan@...tec.com>, Michael Ellerman <mpe@...erman.id.au>
Subject: Re: [v3,11/41] mips: reuse asm-generic/barrier.h

On 01/15/2016 01:57 AM, Will Deacon wrote:
> Paul,
>
>
> I think you figured this out while I was sleeping, but just to confirm:
>
>   1. The MIPS64 ISA doc [1] talks about SYNC in a way that applies only
>      to memory accesses appearing in *program-order* before the SYNC
>
>   2. We need WRC+sync+addr to work, which means that the SYNC in P1 must
>      also capture the store in P0 as being "before" the barrier. Leonid
>      reckons it works, but his explanation [2] focussed on the address
>      dependency in P2 as to why this works. If that is the case (i.e.
>      address dependency provides global transitivity), then WRC+addr+addr
>      should also work (even though its not required).

No, it is not correct. There is one old design which provides access to 
core (thread0 + thread1) write-buffers for threads load in advance of it 
is visible to other cores. It means, that WRC+sync+addr passes because 
of SYNC in write thread and register dependency inside other thread but 
WRC+addr+addr may fail because other core may get a stale data.

>
>   3. It seems that WRC+addr+addr doesn't work, so I'm still suspicious
>      about WRC+sync+addr, because neither the architecture document or
>      Leonid's explanation tell me that it should be forbidden.
>
> Will
>
> [1] https://imgtec.com/?do-download=4302
> [2] http://lkml.kernel.org/r/569565DA.2010903@imgtec.com (scroll to the end)