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Message-ID: <20160115185736.GC31703@Asurada-Nvidia>
Date: Fri, 15 Jan 2016 10:57:36 -0800
From: Nicolin Chen <nicoleotsuka@...il.com>
To: Caleb Crome <caleb@...me.org>
Cc: Timur Tabi <timur@...i.org>, Mark Brown <broonie@...nel.org>,
Xiubo Li <Xiubo.Lee@...il.com>,
Liam Girdwood <lgirdwood@...il.com>,
Jaroslav Kysela <perex@...ex.cz>,
Takashi Iwai <tiwai@...e.com>, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
"alsa-devel@...a-project.org" <alsa-devel@...a-project.org>
Subject: Re: [PATCH RFC 1/1] ASoC: fsl_ssi: Make fifo watermark and maxburst
settings device tree options
On Fri, Jan 15, 2016 at 10:49:04AM -0800, Caleb Crome wrote:
> > The watermark is merely a threshold to trigger a DMA request. The
> > only relationship with the burst size is that each burst transfer
> > should not carry more data than the number of empty slots; FIFO
> > under/overflow occurs otherwise. So it's just more efficient and
> > safer to set an identical value to both of them. I don't think
> > it will cause functional problems to set TFWM to 4 and burst size
> > to 1 -- It just lets DMA operate in a single data transfer mode.
>
> If there is no penalty for setting maxburst to 1 (or 2 in the case of
> dual fifo I think), then should we just set both the watermark and
> maxburst to 1?
>
> I guess the real difference would be when you're in FIQ mode. In FIQ
> mode, the penalty of an interrupt per word would be pretty bad, but in
> DMA mode, if we just set both to 1, we should be fine, right?
There will be much more overhead drawn by frequent DMA transfers.
I believe you understand the idea -- less burst size then more DMA
request. Each DMA transfer contains a pair of handshaking overhead
according to the bus protocol. Apparently the bus will be wasted
with lots of handshaking section instead of keep dedicated to data
transfer truly. It might work if SSI is the only user of the bus,
which we shouldn't assume.
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