[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20160115024534.GB29132@Asurada-Nvidia>
Date: Thu, 14 Jan 2016 18:45:35 -0800
From: Nicolin Chen <nicoleotsuka@...il.com>
To: Caleb Crome <caleb@...me.org>
Cc: Timur Tabi <timur@...i.org>, Xiubo Li <Xiubo.Lee@...il.com>,
Liam Girdwood <lgirdwood@...il.com>,
Mark Brown <broonie@...nel.org>,
Jaroslav Kysela <perex@...ex.cz>,
Takashi Iwai <tiwai@...e.com>, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
"alsa-devel@...a-project.org" <alsa-devel@...a-project.org>
Subject: Re: [PATCH RFC 1/1] ASoC: fsl_ssi: Make fifo watermark and maxburst
settings device tree options
On Thu, Jan 14, 2016 at 01:26:24PM -0800, Caleb Crome wrote:
> As for optimal settings, I finally came to a setting of 4 for depth &
> maxburst, which will result in more DMA requests, but it's the only
> way that works at 48kHz for me. The default settings is 13 (15 - 2)
> for the ones of the 15 item fifo, which is a pretty dramatic
> difference. I just don't know if other chips will behave badly in
> that case.
What's your final configuration for TFWM0 bits, 4?
Powered by blists - more mailing lists