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Message-ID: <20160115030216.GA18411@rob-hp-laptop>
Date: Thu, 14 Jan 2016 21:02:16 -0600
From: Rob Herring <robh@...nel.org>
To: Maxime Ripard <maxime.ripard@...e-electrons.com>
Cc: Mike Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...eaurora.org>,
David Airlie <airlied@...ux.ie>,
Thierry Reding <thierry.reding@...il.com>,
Philipp Zabel <p.zabel@...gutronix.de>,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org, linux-clk@...r.kernel.org,
dri-devel@...ts.freedesktop.org, linux-sunxi@...glegroups.com,
Laurent Pinchart <laurent.pinchart@...asonboard.com>,
Chen-Yu Tsai <wens@...e.org>,
Hans de Goede <hdegoede@...hat.com>,
Alexander Kaplan <alex@...tthing.co>,
Boris Brezillon <boris.brezillon@...e-electrons.com>,
Wynter Woods <wynter@...tthing.co>,
Thomas Petazzoni <thomas.petazzoni@...e-electrons.com>,
Rob Clark <robdclark@...il.com>,
Daniel Vetter <daniel@...ll.ch>
Subject: Re: [PATCH v2 06/26] clk: sunxi: Add PLL3 clock
On Thu, Jan 14, 2016 at 04:24:49PM +0100, Maxime Ripard wrote:
> The A10 SoCs and relatives have a PLL controller to drive the PLL3 and
> PLL7, clocked from a 3MHz oscillator, that drives the display related
> clocks (GPU, display engine, TCON, etc.)
>
> Add a driver for it.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@...e-electrons.com>
> ---
> Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
Acked-by: Rob Herring <robh@...nel.org>
> drivers/clk/sunxi/Makefile | 1 +
> drivers/clk/sunxi/clk-sun4i-pll3.c | 90 +++++++++++++++++++++++
> 3 files changed, 92 insertions(+)
> create mode 100644 drivers/clk/sunxi/clk-sun4i-pll3.c
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