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Date: Tue, 19 Jan 2016 23:01:46 +0800 From: Chen-Yu Tsai <wens@...e.org> To: P L Sai Krishna <lakshmi.sai.krishna.potthuri@...inx.com> Cc: Michal Simek <michal.simek@...inx.com>, Soren Brinkmann <soren.brinkmann@...inx.com>, Ulf Hansson <ulf.hansson@...aro.org>, Kevin Hao <haokexin@...il.com>, Emil Lenchak <emill@...inx.com>, Tobias Klauser <tklauser@...tanz.ch>, Sudeep Holla <Sudeep.Holla@....com>, Adrian Hunter <adrian.hunter@...el.com>, Jisheng Zhang <jszhang@...vell.com>, "Ivan T. Ivanov" <ivan.ivanov@...aro.org>, Scott Branden <sbranden@...adcom.com>, Vincent Yang <vincent.yang.fujitsu@...il.com>, Haibo Chen <haibo.chen@...escale.com>, Marek Vasut <marex@...x.de>, "ludovic.desroches@...el.com" <ludovic.desroches@...el.com>, Rob Herring <robh+dt@...nel.org>, Pawel Moll <pawel.moll@....com>, Mark Rutland <mark.rutland@....com>, Ian Campbell <ijc+devicetree@...lion.org.uk>, Kumar Gala <galak@...eaurora.org>, Suman Tripathi <stripathi@....com>, Shawn Lin <shawn.lin@...k-chips.com>, devicetree <devicetree@...r.kernel.org>, Harini Katakam <harinik@...inx.com>, "linux-mmc@...r.kernel.org" <linux-mmc@...r.kernel.org>, linux-kernel <linux-kernel@...r.kernel.org>, P L Sai Krishna <lakshmis@...inx.com>, Anirudha Sarangi <anirudh@...inx.com>, Punnaiah Choudary Kalluri <punnaia@...inx.com>, linux-arm-kernel <linux-arm-kernel@...ts.infradead.org> Subject: Re: [LINUX PATCH 1/5] mmc: Workaround for the issue in auto tuning mode. Hi, On Tue, Jan 19, 2016 at 10:17 PM, P L Sai Krishna <lakshmi.sai.krishna.potthuri@...inx.com> wrote: > During the auto tuning mode of SDR104, a couple of transactions > on rx_tap_value which are not incremental or decremental by 1. > Since the DLL supports only increment/decrement by 1 during > dynamic change, observed unexpected delays during both these > transactions. > The first transaction occurs when the tap value > reached 0x1F, it will reset to 0x0 and go till 0x7. This > transaction can be avoided by changing the corecfg_dis1p5xtuningcnt > to 1'b1 which is currently tied to 1'b0 in the RTL. > The second transaction occurs after the tuning is completed. > Once the tuning is done, the tuning fsm in the host controller > calculates the average pattern match and will write the value > on the rx tap value. Therefore observed a transaction from 0x7 to > the final value which need not be a increment/decrement value. > Because of this issue DLL tuning will not be accurate and SDR50, > SDR104 & HS200 modes may not work. > > This patch adds workaround to change the SD clock after > tuning done to provide accurate DLL tuning for SDR50, > SD104 & HS200 modes. > > After receiving the tuning done, program "SDCLK Frequency Select" > of clock control register with a value different from the desired > value. Wait for the "Internal Clock Stable" bit of the clock > control register and program the desired frequency. Does this series apply to any non-Arasan or non-sdhci mmc hosts? The subject does not indicate a specific platform. Thanks ChenYu > Signed-off-by: P L Sai Krishna <lakshmis@...inx.com> > --- > drivers/mmc/host/sdhci-of-arasan.c | 18 ++++++++++++++++++ > drivers/mmc/host/sdhci-pltfm.c | 3 +++ > drivers/mmc/host/sdhci.c | 5 +++++ > drivers/mmc/host/sdhci.h | 4 ++++ > 4 files changed, 30 insertions(+)
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