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Message-ID: <569EE62E.3040003@huawei.com>
Date: Wed, 20 Jan 2016 09:43:10 +0800
From: xuejiancheng <xuejiancheng@...wei.com>
To: Rob Herring <robh@...nel.org>
CC: <mturquette@...libre.com>, <sboyd@...eaurora.org>,
<p.zabel@...gutronix.de>, <pawel.moll@....com>,
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<xuwei5@...ilicon.com>, <haojian.zhuang@...aro.org>,
<zhangfei.gao@...aro.org>, <bintian.wang@...wei.com>,
<linux-kernel@...r.kernel.org>, <linux-clk@...r.kernel.org>,
<devicetree@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>, <yanhaifeng@...ilicon.com>,
<yanghongwei@...ilicon.com>, <suwenping@...ilicon.com>,
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<xuejiancheng@...ilicon.com>
Subject: Re: [PATCH v6 1/6] clk: hisilicon: add CRG driver for hi3519 soc
On 2016/1/20 2:23, Rob Herring wrote:
> On Tue, Jan 19, 2016 at 10:38:26AM +0800, Jiancheng Xue wrote:
>> The CRG(Clock and Reset Generator) block provides clock
>> and reset signals for other modules in hi3519 soc.
>>
>> Signed-off-by: Jiancheng Xue <xuejiancheng@...wei.com>
>> ---
>> .../devicetree/bindings/clock/hi3519-crg.txt | 46 +++++++
>
> I already acked this. Please add ack's when posting new versions.
>
> Acked-by: Rob Herring <robh@...nel.org>
>
Hi Rob,
I see. Thank you very much.
Regards,
Jiancheng
>> drivers/clk/hisilicon/Kconfig | 7 ++
>> drivers/clk/hisilicon/Makefile | 2 +
>> drivers/clk/hisilicon/clk-hi3519.c | 132 +++++++++++++++++++++
>> drivers/clk/hisilicon/clk.c | 23 ++--
>> drivers/clk/hisilicon/clk.h | 14 +--
>> drivers/clk/hisilicon/reset.c | 130 ++++++++++++++++++++
>> drivers/clk/hisilicon/reset.h | 32 +++++
>> include/dt-bindings/clock/hi3519-clock.h | 40 +++++++
>> 9 files changed, 411 insertions(+), 15 deletions(-)
>> create mode 100644 Documentation/devicetree/bindings/clock/hi3519-crg.txt
>> create mode 100644 drivers/clk/hisilicon/clk-hi3519.c
>> create mode 100644 drivers/clk/hisilicon/reset.c
>> create mode 100644 drivers/clk/hisilicon/reset.h
>> create mode 100644 include/dt-bindings/clock/hi3519-clock.h
>
> .
>
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