linux-kernel - RE: [RFC] spi-nor: fix cross die reads on Micron multi-die devices

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Date:	Fri, 22 Jan 2016 07:00:43 +0000
From:	Bean Huo 霍斌斌 (beanhuo) 
	<beanhuo@...ron.com>
To:	Boris Brezillon <boris.brezillon@...e-electrons.com>
CC:	Adam Somerville <adamsomerville@...il.com>,
	David Woodhouse <dwmw2@...radead.org>,
	Brian Norris <computersforpeace@...il.com>,
	"linux-mtd@...ts.infradead.org" <linux-mtd@...ts.infradead.org>,
	"zajec5@...il.com" <zajec5@...il.com>,
	"jteki@...nedev.com" <jteki@...nedev.com>,
	"mika.westerberg@...ux.intel.com" <mika.westerberg@...ux.intel.com>,
	"furquan@...gle.com" <furquan@...gle.com>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: RE: [RFC] spi-nor: fix cross die reads on Micron multi-die devices

> Hi Bean,
> 
> On Thu, 21 Jan 2016 01:06:48 +0000
> Bean Huo 霍斌斌 (beanhuo) <beanhuo@...ron.com> wrote:
> 
> >  Hi, Adam and Boris
> >
> > For Micron MT25Q ,MT25T and MT35Q, they does not exist this action
> > even they are Multi-die devices. So when the last byte of the die
> > selected is read, the next byte output is the first byte of next die(not the
> same die).
> > You can check this by extended address register chapter in our
> > datasheet, there are detail Information.
> 
> I never said you were wrong ;), I just asked if it was relevant to differentiate
> the two cases. IOW, would the implementation proposed by Adam work
> correctly on all chips? And what is the real performance penalty for
> MT25Q ,MT25T and MT35Q if we decide to split the read command in several
> reads to handle this cross die case?
For this , performance penalty is tiny, can ignore. 
SPI NOR read performance only depends on SPI I/O clock. Not the same as NAND.
> Best Regards,
> 
> Boris
> 
> --
> Boris Brezillon, Free Electrons
> Embedded Linux and Kernel engineering
> http://free-electrons.com