linux-kernel - Re: [PATCH] mtd: bcm47xxsflash: use devm_ioremap

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Message-ID: <alpine.DEB.2.00.1601242226010.5958@tp.orcam.me.uk>
Date:	Sun, 24 Jan 2016 23:07:54 +0000
From:	"Maciej W. Rozycki" <macro@...tec.com>
To:	Rafał Miłecki <zajec5@...il.com>
CC:	Brian Norris <computersforpeace@...il.com>,
	Ralf Baechle <ralf@...ux-mips.org>,
	Javier Martinez Canillas <javier@....samsung.com>,
	Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
	Fengguang Wu <fengguang.wu@...el.com>,
	Michael Ellerman <mpe@...erman.id.au>,
	Luis de Bethencourt <luisbg@....samsung.com>,
	Jeremy Kerr <jk@...abs.org>,
	Neelesh Gupta <neelegup@...ux.vnet.ibm.com>,
	"linux-mtd@...ts.infradead.org" <linux-mtd@...ts.infradead.org>,
	David Woodhouse <dwmw2@...radead.org>,
	Cyril Bur <cyrilbur@...il.com>,
	"Maciej W. Rozycki" <macro@...ux-mips.org>
Subject: Re: [PATCH] mtd: bcm47xxsflash: use devm_ioremap_nocache() instead
 of KSEG0ADDR()

On Sun, 24 Jan 2016, Rafał Miłecki wrote:

> On 24 January 2016 at 21:26, Maciej W. Rozycki <macro@...tec.com> wrote:
> > On Sat, 23 Jan 2016, Brian Norris wrote:
> >
> >> IIUC, this could be solved by:
> >> (a) using an uncached mapping or
> >> (b) explicitly invalidating the relevant region after doing flash writes
> >> or erasures
> >
> >  Flash writes are usually much, much less frequent than reads, so
> > optimising for reads is IMO the right direction.  So a cached mapping is a
> > good choice, however invalidation must then be done after a write.
> 
> Can you give me some hint where to look at for cache invalidation?

 There is `flush_data_cache_page' only it would seem, which is also 
supported by the MIPS platform only.  It makes unnecessary writebacks 
before invalidation, however these aren't really supposed to happen as no 
cache line involved is expected to be dirty.

 Implementing `invalidate_data_cache_page', which would avoid these 
unnecessary writebacks, should be straightforward as hardware provides the 
necessary operations and actually the MIPS port has suitable low-level 
helpers already implemented, for use by `dma_cache_inv'.  So that would 
merely be a semi-mechanical copy, paste, rename operation applied to our 
source.

 The bigger problem is the lack of portability of this interface to other 
platforms, although I suspect some hardware may simply fail to provide 
required operations.  For example x86 only defines the sledgehammer 
INVD/WBINVD instructions, which operate on the whole cache hierarchy at 
once rather than on a line-by-line and cache level/part basis.

  Maciej