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Message-ID: <20160125122415.GB20452@ulmo.nvidia.com>
Date: Mon, 25 Jan 2016 13:24:15 +0100
From: Thierry Reding <thierry.reding@...il.com>
To: Masahiro Yamada <yamada.masahiro@...ionext.com>
Cc: linux-arm-kernel@...ts.infradead.org, linux-tegra@...r.kernel.org,
Alexandre Courbot <gnurou@...il.com>,
Arnd Bergmann <arnd@...db.de>,
Stephen Warren <swarren@...dotorg.org>,
Mikko Perttunen <mikko.perttunen@...si.fi>,
linux-kernel@...r.kernel.org,
Tuomas Tynkkynen <ttynkkynen@...dia.com>
Subject: Re: [PATCH] ARM: tegra: remove redundant ARM_L1_CACHE_SHIFT_6 select
On Sat, Jan 23, 2016 at 05:55:30PM +0900, Masahiro Yamada wrote:
> These two are both ARMv7 SoCs. They need not explicitly select
> ARM_L1_CACHE_SHIFT_6 because it is enabled along with CPU_V7.
>
> Refer to commit a092f2b15399 ("ARM: 7291/1: cache: assume 64-byte L1
> cachelines for ARMv7 CPUs").
>
> Signed-off-by: Masahiro Yamada <yamada.masahiro@...ionext.com>
> ---
>
> drivers/soc/tegra/Kconfig | 2 --
> 1 file changed, 2 deletions(-)
Applied, thanks.
Thierry
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