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Message-ID: <20160125134953.GK1490@localhost.localdomain>
Date:	Mon, 25 Jan 2016 13:49:53 +0000
From:	Charles Keepax <ckeepax@...nsource.wolfsonmicro.com>
To:	Mans Rullgard <mans@...sr.com>
CC:	Mark Brown <broonie@...nel.org>,
	Liam Girdwood <lgirdwood@...il.com>,
	Jaroslav Kysela <perex@...ex.cz>,
	Takashi Iwai <tiwai@...e.com>,
	<patches@...nsource.wolfsonmicro.com>,
	<alsa-devel@...a-project.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] ASoC: wm8974: configure pll and mclk divider
 automatically

On Mon, Jan 25, 2016 at 12:36:43PM +0000, Mans Rullgard wrote:
> This adds a set_sysclk() DAI op so the card driver can set the
> input clock frequency.  If this is done, the pll and mclk divider
> are configured to produce the required 256x fs clock when the
> sample rate is set by hw_params().
> 
> These additions make the codec work with the simple-card driver.
> Card drivers calling set_pll() and set_clkdiv() directly are
> unaffected.
> 
> Signed-off-by: Mans Rullgard <mans@...sr.com>
> ---

Acked-by: Charles Keepax <ckeepax@...nsource.wolfsonmicro.com>

Thanks,
Charles

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