linux-kernel - Re: [PATCH] powerpc/perf: Remove PPMU_HAS

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Date:	Wed, 27 Jan 2016 15:10:31 +1100
From:	Michael Ellerman <mpe@...erman.id.au>
To:	Madhavan Srinivasan <maddy@...ux.vnet.ibm.com>
Cc:	benh@...nel.crashing.org, linux-kernel@...r.kernel.org,
	linuxppc-dev@...ts.ozlabs.org
Subject: Re: [PATCH]  powerpc/perf: Remove PPMU_HAS_SSLOT flag for Power8

On Mon, 2016-01-25 at 14:03 +0530, Madhavan Srinivasan wrote:

>  Commit: 7a7868326d77 introduced PPMU_HAS_SSLOT flag to
>  remove assumption of MMCRA[SLOT] with respect to
>  PPMU_ALT_SIPR flag. Commit 7a7868326d77's message also
>  specifies that Power8 does not support MMCRA[SLOT].
>  But still PPMU_HAS_SSLOT flag managed to get into
>  Power8 code. Patch to remove the same from Power8 flags.
>
> Signed-off-by: Madhavan Srinivasan <maddy@...ux.vnet.ibm.com>

Thanks.

I cleaned up and expanded the change log:

  powerpc/perf: Remove PPMU_HAS_SSLOT flag for Power8

  Commit 7a7868326d77 ("powerpc/perf: Add an explict flag indicating
  presence of SLOT field") introduced the PPMU_HAS_SSLOT flag to remove
  the assumption that MMCRA[SLOT] was present when PPMU_ALT_SIPR was not
  set.

  That commit's changelog also mentions that Power8 does not support
  MMCRA[SLOT]. However when the Power8 PMU support was merged, it
  errnoeously included the PPMU_HAS_SSLOT flag.

  So remove PPMU_HAS_SSLOT from the Power8 flags.

  mpe: On systems where MMCRA[SLOT] exists, the field occupies bits 37:39
  (IBM numbering). On Power8 bit 37 is reserved, and 38:39 overlap with
  the high bits of the Threshold Event Counter Mantissa. I am not aware of
  any published events which use the thereshold counting mechanism, which
  would cause the mantissa bits to be set. So in practice this bug is
  unlikely to trigger in practice.

  Fixes: e05b9b9e5c10 ("powerpc/perf: Power8 PMU support")
  Signed-off-by: Madhavan Srinivasan <maddy@...ux.vnet.ibm.com>
  Signed-off-by: Michael Ellerman <mpe@...erman.id.au>

cheers