linux-kernel - Re: [PATCH V2 3/4] 8250: 8250_f81504: Add Fintek F81504/508/512 PCIE-to-UART/GPIO UART support

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20160128101702.1b570e1b@lxorguk.ukuu.org.uk>
Date:	Thu, 28 Jan 2016 10:17:02 +0000
From:	One Thousand Gnomes <gnomes@...rguk.ukuu.org.uk>
To:	Peter Hung <hpeter@...il.com>
Cc:	linus.walleij@...aro.org, gnurou@...il.com,
	gregkh@...uxfoundation.org, andriy.shevchenko@...ux.intel.com,
	paul.gortmaker@...driver.com, lee.jones@...aro.org,
	jslaby@...e.com, peter_hong@...tek.com.tw,
	heikki.krogerus@...ux.intel.com, peter@...leysoftware.com,
	soeren.grunewald@...y.de, udknight@...il.com,
	adam.lee@...onical.com, arnd@...db.de, manabian@...il.com,
	scottwood@...escale.com, yamada.masahiro@...ionext.com,
	paul.burton@...tec.com, mans@...sr.com, matthias.bgg@...il.com,
	ralf@...ux-mips.org, linux-kernel@...r.kernel.org,
	linux-gpio@...r.kernel.org, linux-serial@...r.kernel.org,
	tom_tsai@...tek.com.tw, Peter Hung <hpeter+linux_kernel@...il.com>
Subject: Re: [PATCH V2 3/4] 8250: 8250_f81504: Add Fintek F81504/508/512
 PCIE-to-UART/GPIO UART support

On Thu, 28 Jan 2016 17:20:37 +0800
Peter Hung <hpeter@...il.com> wrote:

> This driver is 8250 driver for F81504/508/512, it'll handle the serial
> port operation of this device. This module will depend on
> MFD_FINTEK_F81504_CORE.
> 
> The serial ports support from 50bps to 1.5Mbps with Linux baudrate
> define excluding 1.0Mbps due to not support 16MHz clock source.
> 
> PCI Configuration Space Registers, set:0~11(Max):
>     40h + 8 * set:
>                    bit7~6: Clock source selector
>                        00: 1.8432MHz
>                        01: 18.432MHz
>                        10: 24MHz
>                        11: 14.769MHz
>                    bit0: UART enable
>     41h + 8 * set:
>                    bit5~4: RX trigger multiple
>                        00: 1x * trigger level
>                        01: 2x * trigger level
>                        10: 4x * trigger level
>                        11: 8x * trigger level
>                    bit1~0: FIFO Size
>                        11: 128Bytes
>     44h + 8 * set: UART IO address (LSB)
>     45h + 8 * set: UART IO address (MSB)
>     47h + 8 * set:
>                    bit5: RTS invert (bit4 must enable)
>                    bit4: RTS auto direction enable
>                          0: RTS control by MCR
>                          1: RTS driven high when TX, otherwise low
> 
> Suggested-by: One Thousand Gnomes <gnomes@...rguk.ukuu.org.uk>
> Suggested-by: Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
> Signed-off-by: Peter Hung <hpeter+linux_kernel@...il.com>

Nice

It and the GPIO driver parts

Reviewed-by: Alan Cox <gnomes@...rguk.ukuu.org.uk>

Alan