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Message-ID: <20160128111818.GH17123@leverpostej>
Date: Thu, 28 Jan 2016 11:18:19 +0000
From: Mark Rutland <mark.rutland@....com>
To: Will Deacon <will.deacon@....com>
Cc: Suravee Suthikulpanit <Suravee.Suthikulpanit@....com>,
robin.murphy@....com, robh+dt@...nel.org, pawel.moll@....com,
ijc+devicetree@...lion.org.uk, galak@...eaurora.org, arnd@...db.de,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, arm@...nel.org,
brijeshkumar.singh@....com, thomas.lendacky@....com,
leo.duran@....com
Subject: Re: [PATCH 11/13] dtb: amd: Add PCIe SMMU device tree node
On Thu, Jan 28, 2016 at 11:17:39AM +0000, Will Deacon wrote:
> On Thu, Jan 28, 2016 at 11:14:53AM +0000, Mark Rutland wrote:
> > On Wed, Jan 27, 2016 at 03:11:59PM -0600, Suravee Suthikulpanit wrote:
> > > From: Suravee Suthikulpanit <suravee.suthikulpanit@....com>
> > >
> > > Add PCIe SMMU device tree node for AMD Seattle SOC.
> > >
> > > Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@....com>
> > > ---
> > > arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi | 23 +++++++++++++++++++++++
> > > 1 file changed, 23 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi b/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi
> > > index a7fc059..bfccfea 100644
> > > --- a/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi
> > > +++ b/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi
> > > @@ -210,6 +210,7 @@
> > > device_type = "pci";
> > > bus-range = <0 0x7f>;
> > > msi-parent = <&v2m0>;
> > > + #stream-id-cells = <16>;
> > > reg = <0 0xf0000000 0 0x10000000>;
> > >
> > > interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
> > > @@ -230,6 +231,28 @@
> > > <0x03000000 0x01 0x00000000 0x01 0x00000000 0x7f 0x00000000>;
> > > };
> > >
> > > + pcie0_smmu: smmu@...00000 {
> > > + compatible = "arm,mmu-401";
> > > + reg = <0 0xe0a00000 0 0x10000>;
> > > + #global-interrupts = <1>;
> > > + interrupts = /* Uses combined intr for both
> > > + * global and context
> > > + */
> > > + <0 333 4>,
> > > + <0 333 4>;
> > > + /* Note:
> > > + * SID[2:0] = PCIe function number
> > > + * SID[7:3] = PCIe device number
> > > + * SID[14:8] = PCIe bus number
> > > + */
> > > + mmu-masters = <&pcie0
> > > + /* 1:00:[0,3] */ 256 257 258 259
> > > + /* 2:00:[0,3] */ 512 513 514 515
> > > + /* 3:00:[0,3] */ 768 769 770 771
> > > + /* 4:00:[0,3] */ 1024 1025 1026 1027
> > > + >;
> > > + };
> >
> > This doesn't look right to me.
> >
> > I didn't think that RID->SID mapping was actually defined by any
> > binding, so (how) are these numbers used?
> >
> > I'm uncomfortable with this, given we should be moving towards the
> > generic IOMMU binding (and then we'd use the iommu-map binding [1] for
> > this).
> >
> > Will, Robin, thoughts?
>
> The driver currently assumes a 1:1 RID:SID mapping when it sees a PCI
> device, so those numbers should be ignored.
Given that, they shouldn't be in the DT, then?
Mark.
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