lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20160128174858.GU17123@leverpostej>
Date:	Thu, 28 Jan 2016 17:48:59 +0000
From:	Mark Rutland <mark.rutland@....com>
To:	Robin Murphy <robin.murphy@....com>
Cc:	Anup Patel <anup.patel@...adcom.com>,
	Catalin Marinas <catalin.marinas@....com>,
	Joerg Roedel <joro@...tes.org>,
	Will Deacon <will.deacon@....com>,
	Sricharan R <sricharan@...eaurora.org>,
	Linux IOMMU <iommu@...ts.linux-foundation.org>,
	Linux ARM Kernel <linux-arm-kernel@...ts.infradead.org>,
	Rob Herring <robh+dt@...nel.org>,
	Pawel Moll <pawel.moll@....com>,
	Ian Campbell <ijc+devicetree@...lion.org.uk>,
	Kumar Gala <galak@...eaurora.org>,
	Device Tree <devicetree@...r.kernel.org>,
	Ray Jui <rjui@...adcom.com>,
	Scott Branden <sbranden@...adcom.com>,
	Vikram Prakash <vikramp@...adcom.com>,
	Linux Kernel <linux-kernel@...r.kernel.org>,
	BCM Kernel Feedback <bcm-kernel-feedback-list@...adcom.com>
Subject: Re: [RFC PATCH 4/6] iommu/arm-smmu: Add support for IOMMU_DOMAIN_DMA
 in SMMUv1/SMMUv2 driver

On Thu, Jan 28, 2016 at 05:28:30PM +0000, Robin Murphy wrote:
> On 27/01/16 05:21, Anup Patel wrote:
> >To allow use of large memory (> 4Gb) with 32bit devices we need to use
> >some kind of iommu for such 32bit devices.
> >
> >This patch extends SMMUv1/SMMUv2 driver to support DMA domains which
> >in-turn will allows us to use iommu based DMA mappings for 32bit devices.
> >
> >Signed-off-by: Anup Patel <anup.patel@...adcom.com>
> >Reviewed-by: Ray Jui <rjui@...adcom.com>
> >Reviewed-by: Scott Branden <sbranden@...adcom.com>
> >---
> >  drivers/iommu/arm-smmu.c | 21 ++++++++++++++++++++-
> >  1 file changed, 20 insertions(+), 1 deletion(-)
> >
> >diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
> >index 9bdf6b2..43424fe 100644
> >--- a/drivers/iommu/arm-smmu.c
> >+++ b/drivers/iommu/arm-smmu.c
> >@@ -29,6 +29,7 @@
> >  #define pr_fmt(fmt) "arm-smmu: " fmt
> >
> >  #include <linux/delay.h>
> >+#include <linux/dma-iommu.h>
> >  #include <linux/dma-mapping.h>
> >  #include <linux/err.h>
> >  #include <linux/interrupt.h>
> >@@ -967,7 +968,7 @@ static struct iommu_domain *arm_smmu_domain_alloc(unsigned type)
> >  {
> >  	struct arm_smmu_domain *smmu_domain;
> >
> >-	if (type != IOMMU_DOMAIN_UNMANAGED)
> >+	if (type != IOMMU_DOMAIN_UNMANAGED && type != IOMMU_DOMAIN_DMA)
> >  		return NULL;
> >  	/*
> >  	 * Allocate the domain and initialise some of its data structures.
> >@@ -978,6 +979,12 @@ static struct iommu_domain *arm_smmu_domain_alloc(unsigned type)
> >  	if (!smmu_domain)
> >  		return NULL;
> >
> >+	if (type == IOMMU_DOMAIN_DMA &&
> >+	    iommu_get_dma_cookie(&smmu_domain->domain)) {
> >+		kfree(smmu_domain);
> >+		return NULL;
> >+	}
> >+
> >  	mutex_init(&smmu_domain->init_mutex);
> >  	spin_lock_init(&smmu_domain->pgtbl_lock);
> >
> >@@ -992,6 +999,7 @@ static void arm_smmu_domain_free(struct iommu_domain *domain)
> >  	 * Free the domain resources. We assume that all devices have
> >  	 * already been detached.
> >  	 */
> >+	iommu_put_dma_cookie(domain);
> >  	arm_smmu_destroy_domain_context(domain);
> >  	kfree(smmu_domain);
> >  }
> >@@ -1361,6 +1369,16 @@ static int arm_smmu_init_platform_device(struct device *dev,
> >  	return 0;
> >  }
> >
> >+int arm_smmu_of_xlate(struct device *dev, struct of_phandle_args *args)
> >+{
> >+	/*
> >+	 * Nothing to do here because SMMU is already aware of all
> >+	 * MMU masters and their stream IDs using mmu-master attibute
> >+	 * SMMU DT node.
> >+	 */
> 
> ...but on the same hand this will also never get called if there's
> no "iommus" property on the master. Maintaining support for existing
> users of the "mmu-masters" binding is one thing (namely the thing
> that's been slowing down my efforts to clean up the really hacky
> generic binding support I did all the DMA stuff with), but having
> _both_ bindings in a single DT is something I don't think anybody
> wants to see

Indeed. NAK to the mixed case.

Mark.

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ