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Message-Id: <1454030348-17736-153-git-send-email-kamal@canonical.com>
Date: Thu, 28 Jan 2016 17:18:10 -0800
From: Kamal Mostafa <kamal@...onical.com>
To: linux-kernel@...r.kernel.org, stable@...r.kernel.org,
kernel-team@...ts.ubuntu.com
Cc: Loc Ho <lho@....com>, Stephen Boyd <sboyd@...eaurora.org>,
Kamal Mostafa <kamal@...onical.com>
Subject: [PATCH 3.19.y-ckt 152/210] clk: xgene: Fix divider with non-zero shift value
3.19.8-ckt14 -stable review patch. If anyone has any objections, please let me know.
---8<------------------------------------------------------------
From: Loc Ho <lho@....com>
commit 1382ea631ddddb634850a3795527db0feeff5aaf upstream.
The X-Gene clock driver missed the divider shift operation when
set the divider value.
Signed-off-by: Loc Ho <lho@....com>
Fixes: 308964caeebc ("clk: Add APM X-Gene SoC clock driver")
Signed-off-by: Stephen Boyd <sboyd@...eaurora.org>
Signed-off-by: Kamal Mostafa <kamal@...onical.com>
---
drivers/clk/clk-xgene.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/clk-xgene.c b/drivers/clk/clk-xgene.c
index dd8a62d..1ec5fe8 100644
--- a/drivers/clk/clk-xgene.c
+++ b/drivers/clk/clk-xgene.c
@@ -351,7 +351,8 @@ static int xgene_clk_set_rate(struct clk_hw *hw, unsigned long rate,
/* Set new divider */
data = xgene_clk_read(pclk->param.divider_reg +
pclk->param.reg_divider_offset);
- data &= ~((1 << pclk->param.reg_divider_width) - 1);
+ data &= ~((1 << pclk->param.reg_divider_width) - 1)
+ << pclk->param.reg_divider_shift;
data |= divider;
xgene_clk_write(data, pclk->param.divider_reg +
pclk->param.reg_divider_offset);
--
1.9.1
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