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Message-ID: <1454056197-5893-1-git-send-email-ray.huang@amd.com>
Date:	Fri, 29 Jan 2016 16:29:55 +0800
From:	Huang Rui <ray.huang@....com>
To:	Borislav Petkov <bp@...e.de>,
	Peter Zijlstra <peterz@...radead.org>,
	"Ingo Molnar" <mingo@...nel.org>,
	Andy Lutomirski <luto@...capital.net>,
	"Thomas Gleixner" <tglx@...utronix.de>,
	Robert Richter <rric@...nel.org>,
	Jacob Shin <jacob.w.shin@...il.com>,
	Arnaldo Carvalho de Melo <acme@...nel.org>,
	"Kan Liang" <kan.liang@...el.com>
CC:	<linux-kernel@...r.kernel.org>, <spg_linux_kernel@....com>,
	<x86@...nel.org>,
	Suravee Suthikulpanit <suravee.suthikulpanit@....com>,
	Aravind Gopalakrishnan <Aravind.Gopalakrishnan@....com>,
	Borislav Petkov <bp@...en8.de>,
	Fengguang Wu <fengguang.wu@...el.com>,
	Huang Rui <ray.huang@....com>
Subject: [PATCH 0/2] perf/x86/msr: Add some new AMD performance event counters

Hi all,

This serials of patches add two event counters that are PTSC
(performance time-stamp counter) and IRperf (instructions retired
count) for AMD new processors. They are incicated by
CPUID.8000_0001H:ECX[27] and CPUID.8000_0008H:EBX[1] separately.

Thanks,
Rui

Huang Rui (2):
  perf/x86/msr: Add AMD performance time-stamp counter support
  perf/x86/msr: Add AMD instructions retired performance counter

 arch/x86/include/asm/cpufeature.h    |  2 ++
 arch/x86/include/asm/msr-index.h     |  4 ++++
 arch/x86/kernel/cpu/perf_event_msr.c | 36 ++++++++++++++++++++++++++----------
 3 files changed, 32 insertions(+), 10 deletions(-)

-- 
1.9.1

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