linux-kernel - [tip:ras/core] x86/mce/AMD: Fix LVT offset configuration for thresholding

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Message-ID: <tip-f57a1f3c14b9182f1fea667f5a38a1094699db7c@git.kernel.org>
Date:	Mon, 1 Feb 2016 03:41:35 -0800
From:	tip-bot for Aravind Gopalakrishnan <tipbot@...or.com>
To:	linux-tip-commits@...r.kernel.org
Cc:	linux-kernel@...r.kernel.org, bp@...e.de, peterz@...radead.org,
	torvalds@...ux-foundation.org, linux-edac@...r.kernel.org,
	tony.luck@...el.com, bp@...en8.de, mingo@...nel.org,
	Aravind.Gopalakrishnan@....com, tglx@...utronix.de, hpa@...or.com
Subject: [tip:ras/core] x86/mce/AMD:
  Fix LVT offset configuration for thresholding

Commit-ID:  f57a1f3c14b9182f1fea667f5a38a1094699db7c
Gitweb:     http://git.kernel.org/tip/f57a1f3c14b9182f1fea667f5a38a1094699db7c
Author:     Aravind Gopalakrishnan <Aravind.Gopalakrishnan@....com>
AuthorDate: Mon, 25 Jan 2016 20:41:51 +0100
Committer:  Ingo Molnar <mingo@...nel.org>
CommitDate: Mon, 1 Feb 2016 10:53:57 +0100

x86/mce/AMD: Fix LVT offset configuration for thresholding

For processor families with the Scalable MCA feature, the LVT
offset for threshold interrupts is configured only in MSR
0xC0000410 and not in each per bank MISC register as was done in
earlier families.

Obtain the LVT offset from the correct MSR for those families.

Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@....com>
Signed-off-by: Borislav Petkov <bp@...e.de>
Cc: Borislav Petkov <bp@...en8.de>
Cc: Linus Torvalds <torvalds@...ux-foundation.org>
Cc: Peter Zijlstra <peterz@...radead.org>
Cc: Thomas Gleixner <tglx@...utronix.de>
Cc: Tony Luck <tony.luck@...el.com>
Cc: linux-edac <linux-edac@...r.kernel.org>
Link: http://lkml.kernel.org/r/1453750913-4781-7-git-send-email-bp@alien8.de
Signed-off-by: Ingo Molnar <mingo@...nel.org>
---
 arch/x86/kernel/cpu/mcheck/mce_amd.c | 27 ++++++++++++++++++++++++++-
 1 file changed, 26 insertions(+), 1 deletion(-)

diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c
index 5982227..a77a452 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_amd.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c
@@ -49,6 +49,11 @@
 #define DEF_LVT_OFF		0x2
 #define DEF_INT_TYPE_APIC	0x2
 
+/* Scalable MCA: */
+
+/* Threshold LVT offset is at MSR0xC0000410[15:12] */
+#define SMCA_THR_LVT_OFF	0xF000
+
 static const char * const th_names[] = {
 	"load_store",
 	"insn_fetch",
@@ -142,6 +147,14 @@ static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi)
 	}
 
 	if (apic != msr) {
+		/*
+		 * On SMCA CPUs, LVT offset is programmed at a different MSR, and
+		 * the BIOS provides the value. The original field where LVT offset
+		 * was set is reserved. Return early here:
+		 */
+		if (mce_flags.smca)
+			return 0;
+
 		pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d "
 		       "for bank %d, block %d (MSR%08X=0x%x%08x)\n",
 		       b->cpu, apic, b->bank, b->block, b->address, hi, lo);
@@ -300,7 +313,19 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c)
 				goto init;
 
 			b.interrupt_enable = 1;
-			new	= (high & MASK_LVTOFF_HI) >> 20;
+
+			if (mce_flags.smca) {
+				u32 smca_low, smca_high;
+
+				/* Gather LVT offset for thresholding: */
+				if (rdmsr_safe(MSR_CU_DEF_ERR, &smca_low, &smca_high))
+					break;
+
+				new = (smca_low & SMCA_THR_LVT_OFF) >> 12;
+			} else {
+				new = (high & MASK_LVTOFF_HI) >> 20;
+			}
+
 			offset  = setup_APIC_mce_threshold(offset, new);
 
 			if ((offset == new) &&