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Date: Thu, 4 Feb 2016 19:35:03 +0800 From: Tiffany Lin <tiffany.lin@...iatek.com> To: Hans Verkuil <hans.verkuil@...co.com>, <daniel.thompson@...aro.org>, Rob Herring <robh+dt@...nel.org>, Mauro Carvalho Chehab <mchehab@....samsung.com>, Matthias Brugger <matthias.bgg@...il.com>, Daniel Kurtz <djkurtz@...omium.org>, Pawel Osciak <posciak@...omium.org> CC: Eddie Huang <eddie.huang@...iatek.com>, Yingjoe Chen <yingjoe.chen@...iatek.com>, <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>, <linux-arm-kernel@...ts.infradead.org>, <linux-media@...r.kernel.org>, <linux-mediatek@...ts.infradead.org>, <PoChun.Lin@...iatek.com>, Tiffany Lin <tiffany.lin@...iatek.com> Subject: [PATCH v4 8/8] arm64: dts: mediatek: Add Video Encoder for MT8173 Add video encoder node for MT8173 Signed-off-by: Tiffany Lin <tiffany.lin@...iatek.com> --- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 39 ++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 5b0b38a..f61669d 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -1150,6 +1150,45 @@ clock-names = "apb", "smi"; }; + vcodec_enc: vcodec@...02000 { + compatible = "mediatek,mt8173-vcodec-enc"; + reg = <0 0x18002000 0 0x1000>, /* VENC_SYS */ + <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */ + interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>; + mediatek,larb = <&larb3>, + <&larb5>; + iommus = <&iommu M4U_PORT_VENC_RCPU>, + <&iommu M4U_PORT_VENC_REC>, + <&iommu M4U_PORT_VENC_BSDMA>, + <&iommu M4U_PORT_VENC_SV_COMV>, + <&iommu M4U_PORT_VENC_RD_COMV>, + <&iommu M4U_PORT_VENC_CUR_LUMA>, + <&iommu M4U_PORT_VENC_CUR_CHROMA>, + <&iommu M4U_PORT_VENC_REF_LUMA>, + <&iommu M4U_PORT_VENC_REF_CHROMA>, + <&iommu M4U_PORT_VENC_NBM_RDMA>, + <&iommu M4U_PORT_VENC_NBM_WDMA>, + <&iommu M4U_PORT_VENC_RCPU_SET2>, + <&iommu M4U_PORT_VENC_REC_FRM_SET2>, + <&iommu M4U_PORT_VENC_BSDMA_SET2>, + <&iommu M4U_PORT_VENC_SV_COMA_SET2>, + <&iommu M4U_PORT_VENC_RD_COMA_SET2>, + <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>, + <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>, + <&iommu M4U_PORT_VENC_REF_LUMA_SET2>, + <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>; + mediatek,vpu = <&vpu>; + clocks = <&topckgen CLK_TOP_VENCPLL_D2>, + <&topckgen CLK_TOP_VENC_SEL>, + <&topckgen CLK_TOP_UNIVPLL1_D2>, + <&topckgen CLK_TOP_VENC_LT_SEL>; + clock-names = "vencpll_d2", + "venc_sel", + "univpll1_d2", + "venc_lt_sel"; + }; + vencltsys: clock-controller@...00000 { compatible = "mediatek,mt8173-vencltsys", "syscon"; reg = <0 0x19000000 0 0x1000>; -- 1.7.9.5
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