linux-kernel - Re: [PATCH] MIPS: Stop using dla in 32 bit kernels

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Message-ID: <20160204151833.GE18491@linux-mips.org>
Date:	Thu, 4 Feb 2016 16:18:34 +0100
From:	Ralf Baechle <ralf@...ux-mips.org>
To:	Paul Burton <paul.burton@...tec.com>
Cc:	linux-mips@...ux-mips.org, linux-kernel@...r.kernel.org,
	James Hogan <james.hogan@...tec.com>,
	"Maciej W. Rozycki" <macro@...ux-mips.org>
Subject: Re: [PATCH] MIPS: Stop using dla in 32 bit kernels

On Thu, Feb 04, 2016 at 02:31:57PM +0000, Paul Burton wrote:

>       CC      arch/mips/mm/c-r4k.o
>     {standard input}: Assembler messages:
>     {standard input}:4105: Warning: dla used to load 32-bit register;
>         recommend using la instead
>     {standard input}:4129: Warning: dla used to load 32-bit register;
>         recommend using la instead

Sigh.  Another new binutils warning?

> Avoid this by instead making use of the PTR_LA macro which defines the
> appropriate variant of the "la" instruction to use.
> 
> Tested with Codescape GNU Tools 2015.06-05 for MIPS IMG Linux, which
> includes binutils 2.24.90 & gcc 4.9.2.

> @@ -54,22 +55,16 @@
>  
>  /*
>   * gcc has a tradition of misscompiling the previous construct using the
> - * address of a label as argument to inline assembler.	Gas otoh has the
> - * annoying difference between la and dla which are only usable for 32-bit
> - * rsp. 64-bit code, so can't be used without conditional compilation.
> - * The alterantive is switching the assembler to 64-bit code which happens
> - * to work right even for 32-bit code ...
> + * address of a label as argument to inline assembler.
>   */
>  #define instruction_hazard()						\
>  do {									\
>  	unsigned long tmp;						\
>  									\
>  	__asm__ __volatile__(						\
> -	"	.set "MIPS_ISA_LEVEL"				\n"	\
> -	"	dla	%0, 1f					\n"	\
> -	"	jr.hb	%0					\n"	\
> -	"	.set	mips0					\n"	\
> -	"1:							\n"	\
> +	__stringify(PTR_LA) "	%0, 1f\n\t"				\
> +	"jr.hb	%0\n\t"							\
> +	"1:"								\
>  	: "=r" (tmp));							\
>  } while (0)


The .set will need to stay or this will fail up on older processors
with

/tmp/ccKNXiPT.s:21: Error: opcode not supported on this processor: mips1 (mips1) `jr.hb '

The opcode of JR.HB will by older processors be treated as just a JR afair.

Or with less inline assembler obscurities something like:

void foo(void)
{
        void *jr = &&jr;

        __asm__ __volatile__(
	"       .set	"MIPS_ISA_LEVEL"				\n"
        "       jr.hb							\n"
	"	.set	mips0						\n"
        : /* no outputs */
        : "r" (jr));
jr:     ;
}

Now GCC can even schedule loading the address or do other clever things.

  Ralf