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Message-ID: <1454602213-967-6-git-send-email-paul.burton@imgtec.com>
Date: Thu, 4 Feb 2016 16:10:12 +0000
From: Paul Burton <paul.burton@...tec.com>
To: <linux-mips@...ux-mips.org>
CC: Bharat Kumar Gogada <bharatku@...inx.com>,
Michal Simek <michal.simek@...inx.com>,
Ravikiran Gummaluri <rgummal@...inx.com>,
"Paul Burton" <paul.burton@...tec.com>,
Sören Brinkmann <soren.brinkmann@...inx.com>,
Jiang Liu <jiang.liu@...ux.intel.com>,
"Lorenzo Pieralisi" <lorenzo.pieralisi@....com>,
Grygorii Strashko <grygorii.strashko@...com>,
Russell Joyce <russell.joyce@...k.ac.uk>,
"Bjorn Helgaas" <bhelgaas@...gle.com>, <linux-pci@...r.kernel.org>,
<linux-kernel@...r.kernel.org>,
Thomas Gleixner <tglx@...utronix.de>,
"Jingoo Han" <jingoohan1@...il.com>,
<linux-arm-kernel@...ts.infradead.org>
Subject: [PATCH v3 5/6] PCI: xilinx: Fix INTX irq dispatch
The IRQ domain for INTX interrupts has 4 entries, numbered 0 to 3. This
matches what the hardware reports from the interrupt FIFO exactly, but
xilinx_pcie_intr_handler was adding 1 to that value to convert to the
range 1 to 4. Stop adding 1, such that all of INTA through to INTD fall
within the range of the IRQ domain.
Signed-off-by: Paul Burton <paul.burton@...tec.com>
Fixes: 8961def56845 ("PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver")
---
Changes in v3:
- Split out from Boston patchset.
Changes in v2:
- Add Fixes tag.
drivers/pci/host/pcie-xilinx.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c
index 6c5a503..8013e83 100644
--- a/drivers/pci/host/pcie-xilinx.c
+++ b/drivers/pci/host/pcie-xilinx.c
@@ -451,8 +451,8 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data)
irq = pcie_read(port, XILINX_PCIE_REG_RPIFR2) &
XILINX_PCIE_RPIFR2_MSG_DATA;
} else {
- val = ((val & XILINX_PCIE_RPIFR1_INTR_MASK) >>
- XILINX_PCIE_RPIFR1_INTR_SHIFT) + 1;
+ val = (val & XILINX_PCIE_RPIFR1_INTR_MASK) >>
+ XILINX_PCIE_RPIFR1_INTR_SHIFT;
irq = irq_find_mapping(port->irq_domain, val);
}
--
2.7.0
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