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Message-ID: <56B4DA8B.2050609@amd.com>
Date: Fri, 5 Feb 2016 11:23:23 -0600
From: Brijesh Singh <brijesh.singh@....com>
To: Arnd Bergmann <arnd@...db.de>
CC: <brijesh.singh@....com>, Tejun Heo <tj@...nel.org>,
<linux-kernel@...r.kernel.org>, <hdegoede@...hat.com>,
<linux-ide@...r.kernel.org>, Graeme Gregory <graeme@...a.org.uk>
Subject: Re: [PATCH v2] ata: add AMD Seattle platform driver
Hi,
>> }
>>
>> Windows driver folks were okay to look at second resource field to map the SGPIO register and program the
>> registers to blink the LEDs. I think as per ACPI spec, its legal to pass more than one block in resource
>> template and since AML method is not mandatory for non standard enclosure management hence its entirely
>> possible that some BIOS vendors may not implement it at all. But if they implement and decide
>> to expose either AML method or register map but not both then Windows driver may break.
>
> I don't have access to the Windows source code. Is this in the
> architecture-independent part of their kernel, or only done on ARM64?
> How do they decide what the second memory range is for?
>
> If this is now a de-facto extension to the PCI_CLASS_STORAGE_SATA_AHCI binding,
> it should probably be put into the next version of the AHCI spec, and then
> there is no problem using it.
>
I don't have Windows code either and do not know the implementation details. I was told by the AMD folks
working on Windows drivers for Seattle that they do not need any changes in BIOS DSDT to get the LEDs blinking.
This is not a de-facto extension of SATA_AHCI binding, you can call this method as a SoC hack to support the LEDs.
We are working with whatever BIOS is already available to enable the LEDs blinking.
>
> Arnd
>
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