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Message-ID: <HE1PR02MB138769C4BA48A4D8884BC516D6D60@HE1PR02MB1387.eurprd02.prod.outlook.com>
Date:	Tue, 9 Feb 2016 12:36:35 +0000
From:	Noam Camus <noamc@...hip.com>
To:	Daniel Lezcano <daniel.lezcano@...aro.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
CC:	"linux-snps-arc@...ts.infradead.org" 
	<linux-snps-arc@...ts.infradead.org>,
	"marc.zyngier@....com" <marc.zyngier@....com>,
	Chris Metcalf <cmetcalf@...hip.com>,
	Tal Zilcer <talz@...hip.com>,
	Gilad Ben Yossef <giladb@...hip.com>,
	Rob Herring <robh+dt@...nel.org>,
	Thomas Gleixner <tglx@...utronix.de>,
	John Stultz <john.stultz@...aro.org>
Subject: RE: [PATCH v3 2/3] clocksource: Add NPS400 timers driver

>From: Daniel Lezcano [mailto:daniel.lezcano@...aro.org] 
>Sent: Monday, February 08, 2016 4:22 PM

>> +	ret = clk_prepare_enable(clk);
>> +	if (ret)
>> +		pr_err("Couldn't enable parent clock\n");
>> +
>> +	nps_timer_rate = clk_get_rate(clk);

>If there is an error, you continue the execution of the code. I guess you expect the system to hang in any case with the error in the >console, right ?

Since our clock is root then returned value will always be valid.
I am far from being expert here, but no one checks for clk_get_rate() return value for error.
Could you refer to a single place at clocksource drivers that checks for error in the return value.

>> +	ret = clocksource_register_hz(clksrc, nps_timer_rate);

>You can simplify the driver even more by using clocksource_mmio_init.
Since my base address depends on cluster number, which CPU is part of,  this interface is not much of a use. On top of that it assumes that I am little endian by using readl family accessories.

-Noam

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