| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <20160210161639.GD3782@x1>
Date: Wed, 10 Feb 2016 16:16:39 +0000
From: Lee Jones <lee.jones@...aro.org>
To: Charles Keepax <ckeepax@...nsource.wolfsonmicro.com>
Cc: linux-kernel@...r.kernel.org, patches@...nsource.wolfsonmicro.com
Subject: Re: [PATCH RESEND 1/7] mfd: wm5110: Fix defaults array based on
testing
On Tue, 09 Feb 2016, Charles Keepax wrote:
> My automated test is back and now can check defaults against the actual
> hardware. This patch updates the defaults array for the differences
> detected and removes a couple of completely unused registers.
>
> Signed-off-by: Charles Keepax <ckeepax@...nsource.wolfsonmicro.com>
> ---
> drivers/mfd/wm5110-tables.c | 82 ++++++++++++++++++++-------------------------
> 1 file changed, 37 insertions(+), 45 deletions(-)
Applied, thanks.
> diff --git a/drivers/mfd/wm5110-tables.c b/drivers/mfd/wm5110-tables.c
> index c18e11f..8e74e71 100644
> --- a/drivers/mfd/wm5110-tables.c
> +++ b/drivers/mfd/wm5110-tables.c
> @@ -676,8 +676,8 @@ static const struct reg_default wm5110_reg_default[] = {
> { 0x00000008, 0x0019 }, /* R8 - Ctrl IF SPI CFG 1 */
> { 0x00000009, 0x0001 }, /* R9 - Ctrl IF I2C1 CFG 1 */
> { 0x0000000A, 0x0001 }, /* R10 - Ctrl IF I2C2 CFG 1 */
> - { 0x0000000B, 0x0036 }, /* R11 - Ctrl IF I2C1 CFG 2 */
> - { 0x0000000C, 0x0036 }, /* R12 - Ctrl IF I2C2 CFG 2 */
> + { 0x0000000B, 0x001A }, /* R11 - Ctrl IF I2C1 CFG 2 */
> + { 0x0000000C, 0x001A }, /* R12 - Ctrl IF I2C2 CFG 2 */
> { 0x00000020, 0x0000 }, /* R32 - Tone Generator 1 */
> { 0x00000021, 0x1000 }, /* R33 - Tone Generator 2 */
> { 0x00000022, 0x0000 }, /* R34 - Tone Generator 3 */
> @@ -723,14 +723,12 @@ static const struct reg_default wm5110_reg_default[] = {
> { 0x00000154, 0x0000 }, /* R340 - Rate Estimator 3 */
> { 0x00000155, 0x0000 }, /* R341 - Rate Estimator 4 */
> { 0x00000156, 0x0000 }, /* R342 - Rate Estimator 5 */
> - { 0x00000171, 0x0000 }, /* R369 - FLL1 Control 1 */
> + { 0x00000171, 0x0002 }, /* R369 - FLL1 Control 1 */
> { 0x00000172, 0x0008 }, /* R370 - FLL1 Control 2 */
> { 0x00000173, 0x0018 }, /* R371 - FLL1 Control 3 */
> { 0x00000174, 0x007D }, /* R372 - FLL1 Control 4 */
> { 0x00000175, 0x0006 }, /* R373 - FLL1 Control 5 */
> { 0x00000176, 0x0000 }, /* R374 - FLL1 Control 6 */
> - { 0x00000177, 0x0281 }, /* R375 - FLL1 Loop Filter Test 1 */
> - { 0x00000178, 0x0000 }, /* R376 - FLL1 NCO Test 0 */
> { 0x00000179, 0x0000 }, /* R376 - FLL1 Control 7 */
> { 0x00000181, 0x0000 }, /* R385 - FLL1 Synchroniser 1 */
> { 0x00000182, 0x0000 }, /* R386 - FLL1 Synchroniser 2 */
> @@ -740,15 +738,13 @@ static const struct reg_default wm5110_reg_default[] = {
> { 0x00000186, 0x0000 }, /* R390 - FLL1 Synchroniser 6 */
> { 0x00000187, 0x0001 }, /* R390 - FLL1 Synchroniser 7 */
> { 0x00000189, 0x0000 }, /* R393 - FLL1 Spread Spectrum */
> - { 0x0000018A, 0x0004 }, /* R394 - FLL1 GPIO Clock */
> - { 0x00000191, 0x0000 }, /* R401 - FLL2 Control 1 */
> + { 0x0000018A, 0x000C }, /* R394 - FLL1 GPIO Clock */
> + { 0x00000191, 0x0002 }, /* R401 - FLL2 Control 1 */
> { 0x00000192, 0x0008 }, /* R402 - FLL2 Control 2 */
> { 0x00000193, 0x0018 }, /* R403 - FLL2 Control 3 */
> { 0x00000194, 0x007D }, /* R404 - FLL2 Control 4 */
> { 0x00000195, 0x000C }, /* R405 - FLL2 Control 5 */
> { 0x00000196, 0x0000 }, /* R406 - FLL2 Control 6 */
> - { 0x00000197, 0x0000 }, /* R407 - FLL2 Loop Filter Test 1 */
> - { 0x00000198, 0x0000 }, /* R408 - FLL2 NCO Test 0 */
> { 0x00000199, 0x0000 }, /* R408 - FLL2 Control 7 */
> { 0x000001A1, 0x0000 }, /* R417 - FLL2 Synchroniser 1 */
> { 0x000001A2, 0x0000 }, /* R418 - FLL2 Synchroniser 2 */
> @@ -758,7 +754,7 @@ static const struct reg_default wm5110_reg_default[] = {
> { 0x000001A6, 0x0000 }, /* R422 - FLL2 Synchroniser 6 */
> { 0x000001A7, 0x0001 }, /* R422 - FLL2 Synchroniser 7 */
> { 0x000001A9, 0x0000 }, /* R425 - FLL2 Spread Spectrum */
> - { 0x000001AA, 0x0004 }, /* R426 - FLL2 GPIO Clock */
> + { 0x000001AA, 0x000C }, /* R426 - FLL2 GPIO Clock */
> { 0x00000200, 0x0006 }, /* R512 - Mic Charge Pump 1 */
> { 0x00000210, 0x0184 }, /* R528 - LDO1 Control 1 */
> { 0x00000213, 0x03E4 }, /* R531 - LDO2 Control 1 */
> @@ -771,9 +767,9 @@ static const struct reg_default wm5110_reg_default[] = {
> { 0x000002A3, 0x1102 }, /* R675 - Mic Detect 1 */
> { 0x000002A4, 0x009F }, /* R676 - Mic Detect 2 */
> { 0x000002A6, 0x3737 }, /* R678 - Mic Detect Level 1 */
> - { 0x000002A7, 0x372C }, /* R679 - Mic Detect Level 2 */
> + { 0x000002A7, 0x2C37 }, /* R679 - Mic Detect Level 2 */
> { 0x000002A8, 0x1422 }, /* R680 - Mic Detect Level 3 */
> - { 0x000002A9, 0x300A }, /* R681 - Mic Detect Level 4 */
> + { 0x000002A9, 0x030A }, /* R681 - Mic Detect Level 4 */
> { 0x000002C3, 0x0000 }, /* R707 - Mic noise mix control 1 */
> { 0x000002CB, 0x0000 }, /* R715 - Isolation control */
> { 0x000002D3, 0x0000 }, /* R723 - Jack detect analogue */
> @@ -810,53 +806,53 @@ static const struct reg_default wm5110_reg_default[] = {
> { 0x00000409, 0x0022 }, /* R1033 - Output Volume Ramp */
> { 0x00000410, 0x0080 }, /* R1040 - Output Path Config 1L */
> { 0x00000411, 0x0180 }, /* R1041 - DAC Digital Volume 1L */
> - { 0x00000412, 0x0080 }, /* R1042 - DAC Volume Limit 1L */
> + { 0x00000412, 0x0081 }, /* R1042 - DAC Volume Limit 1L */
> { 0x00000413, 0x0001 }, /* R1043 - Noise Gate Select 1L */
> { 0x00000414, 0x0080 }, /* R1044 - Output Path Config 1R */
> { 0x00000415, 0x0180 }, /* R1045 - DAC Digital Volume 1R */
> - { 0x00000416, 0x0080 }, /* R1046 - DAC Volume Limit 1R */
> + { 0x00000416, 0x0081 }, /* R1046 - DAC Volume Limit 1R */
> { 0x00000417, 0x0002 }, /* R1047 - Noise Gate Select 1R */
> { 0x00000418, 0x0080 }, /* R1048 - Output Path Config 2L */
> { 0x00000419, 0x0180 }, /* R1049 - DAC Digital Volume 2L */
> - { 0x0000041A, 0x0080 }, /* R1050 - DAC Volume Limit 2L */
> + { 0x0000041A, 0x0081 }, /* R1050 - DAC Volume Limit 2L */
> { 0x0000041B, 0x0004 }, /* R1051 - Noise Gate Select 2L */
> { 0x0000041C, 0x0080 }, /* R1052 - Output Path Config 2R */
> { 0x0000041D, 0x0180 }, /* R1053 - DAC Digital Volume 2R */
> - { 0x0000041E, 0x0080 }, /* R1054 - DAC Volume Limit 2R */
> + { 0x0000041E, 0x0081 }, /* R1054 - DAC Volume Limit 2R */
> { 0x0000041F, 0x0008 }, /* R1055 - Noise Gate Select 2R */
> { 0x00000420, 0x0080 }, /* R1056 - Output Path Config 3L */
> { 0x00000421, 0x0180 }, /* R1057 - DAC Digital Volume 3L */
> - { 0x00000422, 0x0080 }, /* R1058 - DAC Volume Limit 3L */
> + { 0x00000422, 0x0081 }, /* R1058 - DAC Volume Limit 3L */
> { 0x00000423, 0x0010 }, /* R1059 - Noise Gate Select 3L */
> { 0x00000424, 0x0080 }, /* R1060 - Output Path Config 3R */
> { 0x00000425, 0x0180 }, /* R1061 - DAC Digital Volume 3R */
> - { 0x00000426, 0x0080 }, /* R1062 - DAC Volume Limit 3R */
> + { 0x00000426, 0x0081 }, /* R1062 - DAC Volume Limit 3R */
> { 0x00000427, 0x0020 }, /* R1063 - Noise Gate Select 3R */
> { 0x00000428, 0x0000 }, /* R1064 - Output Path Config 4L */
> { 0x00000429, 0x0180 }, /* R1065 - DAC Digital Volume 4L */
> - { 0x0000042A, 0x0080 }, /* R1066 - Out Volume 4L */
> + { 0x0000042A, 0x0081 }, /* R1066 - Out Volume 4L */
> { 0x0000042B, 0x0040 }, /* R1067 - Noise Gate Select 4L */
> { 0x0000042C, 0x0000 }, /* R1068 - Output Path Config 4R */
> { 0x0000042D, 0x0180 }, /* R1069 - DAC Digital Volume 4R */
> - { 0x0000042E, 0x0080 }, /* R1070 - Out Volume 4R */
> + { 0x0000042E, 0x0081 }, /* R1070 - Out Volume 4R */
> { 0x0000042F, 0x0080 }, /* R1071 - Noise Gate Select 4R */
> { 0x00000430, 0x0000 }, /* R1072 - Output Path Config 5L */
> { 0x00000431, 0x0180 }, /* R1073 - DAC Digital Volume 5L */
> - { 0x00000432, 0x0080 }, /* R1074 - DAC Volume Limit 5L */
> + { 0x00000432, 0x0081 }, /* R1074 - DAC Volume Limit 5L */
> { 0x00000433, 0x0100 }, /* R1075 - Noise Gate Select 5L */
> { 0x00000434, 0x0000 }, /* R1076 - Output Path Config 5R */
> { 0x00000435, 0x0180 }, /* R1077 - DAC Digital Volume 5R */
> - { 0x00000436, 0x0080 }, /* R1078 - DAC Volume Limit 5R */
> + { 0x00000436, 0x0081 }, /* R1078 - DAC Volume Limit 5R */
> { 0x00000437, 0x0200 }, /* R1079 - Noise Gate Select 5R */
> { 0x00000438, 0x0000 }, /* R1080 - Output Path Config 6L */
> { 0x00000439, 0x0180 }, /* R1081 - DAC Digital Volume 6L */
> - { 0x0000043A, 0x0080 }, /* R1082 - DAC Volume Limit 6L */
> + { 0x0000043A, 0x0081 }, /* R1082 - DAC Volume Limit 6L */
> { 0x0000043B, 0x0400 }, /* R1083 - Noise Gate Select 6L */
> { 0x0000043C, 0x0000 }, /* R1084 - Output Path Config 6R */
> { 0x0000043D, 0x0180 }, /* R1085 - DAC Digital Volume 6R */
> - { 0x0000043E, 0x0080 }, /* R1086 - DAC Volume Limit 6R */
> + { 0x0000043E, 0x0081 }, /* R1086 - DAC Volume Limit 6R */
> { 0x0000043F, 0x0800 }, /* R1087 - Noise Gate Select 6R */
> - { 0x00000440, 0x8FFF }, /* R1088 - DRE Enable */
> + { 0x00000440, 0x003F }, /* R1088 - DRE Enable */
> { 0x00000450, 0x0000 }, /* R1104 - DAC AEC Control 1 */
> { 0x00000458, 0x0000 }, /* R1112 - Noise Gate Control */
> { 0x00000490, 0x0069 }, /* R1168 - PDM SPK1 CTRL 1 */
> @@ -864,8 +860,8 @@ static const struct reg_default wm5110_reg_default[] = {
> { 0x00000492, 0x0069 }, /* R1170 - PDM SPK2 CTRL 1 */
> { 0x00000493, 0x0000 }, /* R1171 - PDM SPK2 CTRL 2 */
> { 0x000004A0, 0x3480 }, /* R1184 - HP1 Short Circuit Ctrl */
> - { 0x000004A1, 0x3480 }, /* R1185 - HP2 Short Circuit Ctrl */
> - { 0x000004A2, 0x3480 }, /* R1186 - HP3 Short Circuit Ctrl */
> + { 0x000004A1, 0x3400 }, /* R1185 - HP2 Short Circuit Ctrl */
> + { 0x000004A2, 0x3400 }, /* R1186 - HP3 Short Circuit Ctrl */
> { 0x00000500, 0x000C }, /* R1280 - AIF1 BCLK Ctrl */
> { 0x00000501, 0x0008 }, /* R1281 - AIF1 Tx Pin Ctrl */
> { 0x00000502, 0x0000 }, /* R1282 - AIF1 Rx Pin Ctrl */
> @@ -1483,23 +1479,23 @@ static const struct reg_default wm5110_reg_default[] = {
> { 0x00000C10, 0x1000 }, /* R3088 - GPIO Debounce Config */
> { 0x00000C18, 0x0000 }, /* R3096 - GP Switch 1 */
> { 0x00000C20, 0x8002 }, /* R3104 - Misc Pad Ctrl 1 */
> - { 0x00000C21, 0x8001 }, /* R3105 - Misc Pad Ctrl 2 */
> + { 0x00000C21, 0x0001 }, /* R3105 - Misc Pad Ctrl 2 */
> { 0x00000C22, 0x0000 }, /* R3106 - Misc Pad Ctrl 3 */
> { 0x00000C23, 0x0000 }, /* R3107 - Misc Pad Ctrl 4 */
> { 0x00000C24, 0x0000 }, /* R3108 - Misc Pad Ctrl 5 */
> { 0x00000C25, 0x0000 }, /* R3109 - Misc Pad Ctrl 6 */
> - { 0x00000C30, 0x8282 }, /* R3120 - Misc Pad Ctrl 7 */
> - { 0x00000C31, 0x0082 }, /* R3121 - Misc Pad Ctrl 8 */
> - { 0x00000C32, 0x8282 }, /* R3122 - Misc Pad Ctrl 9 */
> - { 0x00000C33, 0x8282 }, /* R3123 - Misc Pad Ctrl 10 */
> - { 0x00000C34, 0x8282 }, /* R3124 - Misc Pad Ctrl 11 */
> - { 0x00000C35, 0x8282 }, /* R3125 - Misc Pad Ctrl 12 */
> - { 0x00000C36, 0x8282 }, /* R3126 - Misc Pad Ctrl 13 */
> - { 0x00000C37, 0x8282 }, /* R3127 - Misc Pad Ctrl 14 */
> - { 0x00000C38, 0x8282 }, /* R3128 - Misc Pad Ctrl 15 */
> - { 0x00000C39, 0x8282 }, /* R3129 - Misc Pad Ctrl 16 */
> - { 0x00000C3A, 0x8282 }, /* R3130 - Misc Pad Ctrl 17 */
> - { 0x00000C3B, 0x8282 }, /* R3131 - Misc Pad Ctrl 18 */
> + { 0x00000C30, 0x0404 }, /* R3120 - Misc Pad Ctrl 7 */
> + { 0x00000C31, 0x0004 }, /* R3121 - Misc Pad Ctrl 8 */
> + { 0x00000C32, 0x0404 }, /* R3122 - Misc Pad Ctrl 9 */
> + { 0x00000C33, 0x0404 }, /* R3123 - Misc Pad Ctrl 10 */
> + { 0x00000C34, 0x0404 }, /* R3124 - Misc Pad Ctrl 11 */
> + { 0x00000C35, 0x0404 }, /* R3125 - Misc Pad Ctrl 12 */
> + { 0x00000C36, 0x0404 }, /* R3126 - Misc Pad Ctrl 13 */
> + { 0x00000C37, 0x0404 }, /* R3127 - Misc Pad Ctrl 14 */
> + { 0x00000C38, 0x0004 }, /* R3128 - Misc Pad Ctrl 15 */
> + { 0x00000C39, 0x0404 }, /* R3129 - Misc Pad Ctrl 16 */
> + { 0x00000C3A, 0x0404 }, /* R3130 - Misc Pad Ctrl 17 */
> + { 0x00000C3B, 0x0404 }, /* R3131 - Misc Pad Ctrl 18 */
> { 0x00000D08, 0xFFFF }, /* R3336 - Interrupt Status 1 Mask */
> { 0x00000D09, 0xFFFF }, /* R3337 - Interrupt Status 2 Mask */
> { 0x00000D0A, 0xFFFF }, /* R3338 - Interrupt Status 3 Mask */
> @@ -1641,7 +1637,7 @@ static const struct reg_default wm5110_reg_default[] = {
> { 0x00000F0D, 0x0000 }, /* R3853 - ANC Coefficient */
> { 0x00000F0E, 0x0000 }, /* R3854 - ANC Coefficient */
> { 0x00000F0F, 0x0000 }, /* R3855 - ANC Coefficient */
> - { 0x00000F10, 0x0000 }, /* R3856 - ANC Coefficient */
> + { 0x00000F10, 0x0001 }, /* R3856 - ANC Coefficient */
> { 0x00000F11, 0x0000 }, /* R3857 - ANC Coefficient */
> { 0x00000F12, 0x0000 }, /* R3858 - ANC Coefficient */
> { 0x00000F15, 0x0000 }, /* R3861 - FCL Filter Control */
> @@ -1947,8 +1943,6 @@ static bool wm5110_readable_register(struct device *dev, unsigned int reg)
> case ARIZONA_FLL1_CONTROL_5:
> case ARIZONA_FLL1_CONTROL_6:
> case ARIZONA_FLL1_CONTROL_7:
> - case ARIZONA_FLL1_LOOP_FILTER_TEST_1:
> - case ARIZONA_FLL1_NCO_TEST_0:
> case ARIZONA_FLL1_SYNCHRONISER_1:
> case ARIZONA_FLL1_SYNCHRONISER_2:
> case ARIZONA_FLL1_SYNCHRONISER_3:
> @@ -1965,8 +1959,6 @@ static bool wm5110_readable_register(struct device *dev, unsigned int reg)
> case ARIZONA_FLL2_CONTROL_5:
> case ARIZONA_FLL2_CONTROL_6:
> case ARIZONA_FLL2_CONTROL_7:
> - case ARIZONA_FLL2_LOOP_FILTER_TEST_1:
> - case ARIZONA_FLL2_NCO_TEST_0:
> case ARIZONA_FLL2_SYNCHRONISER_1:
> case ARIZONA_FLL2_SYNCHRONISER_2:
> case ARIZONA_FLL2_SYNCHRONISER_3:
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
Powered by blists - more mailing lists