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Message-ID: <CACRpkdbKVVxFs7aSE_2gRgtNSUJ0hsE++FATyD6uWcwxXvTjTw@mail.gmail.com>
Date: Thu, 11 Feb 2016 14:30:57 +0100
From: Linus Walleij <linus.walleij@...aro.org>
To: Krzysztof Adamski <krzysztof.adamski@...to.com>
Cc: Maxime Ripard <maxime.ripard@...e-electrons.com>,
Chen-Yu Tsai <wens@...e.org>,
Hans de Goede <hdegoede@...hat.com>,
Lee Jones <lee@...nel.org>, Rob Herring <robh@...nel.org>,
Jens Kuske <jenskuske@...il.com>,
Fabian Frederick <fabf@...net.be>,
Vishnu Patekar <vishnupatekar0510@...il.com>,
"linux-gpio@...r.kernel.org" <linux-gpio@...r.kernel.org>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
linux-sunxi <linux-sunxi@...glegroups.com>,
Krzysztof Adamski <k@...ko.eu>
Subject: Re: [PATCH v4 5/5] pinctrl: sunxi: Use pin number when calling sunxi_pmx_set
On Tue, Feb 9, 2016 at 3:58 PM, Krzysztof Adamski
<krzysztof.adamski@...to.com> wrote:
> sunxi_pmx_set accepts pin number and then calculates offset by
> subtracting pin_base from it. sunxi_pinctrl_gpio_get, on the other hand,
> gets offset so we have to convert it to pin number so we won't get
> negative value in sunxi_pmx_set.
>
> This was only used on A10 so far, where there is only one GPIO chip with
> pin_base set to 0 so it didn't matter. However H3 also requires this
> workaround but have two pinmux sections, triggering problem for PL port.
>
> Signed-off-by: Krzysztof Adamski <k@...ko.eu>
> Acked-by: Chen-Yu Tsai <wens@...e.org>
> Acked-by: Maxime Ripard <maxime.ripard@...e-electrons.com>
OK applied this version that has Maxime's ACK.
Yours,
Linus Walleij
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