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Message-Id: <2686b3bbb9ec1c86828b365645bd7f997a9780b4.1455206007.git.larper@axis.com>
Date: Thu, 11 Feb 2016 17:01:03 +0100
From: Lars Persson <lars.persson@...s.com>
To: devicetree@...r.kernel.org, linux-clk@...r.kernel.org
Cc: mturquette@...libre.com, sboyd@...eaurora.org, robh+dt@...nel.org,
pawel.moll@....com, mark.rutland@....com,
ijc+devicetree@...lion.org.uk, galak@...eaurora.org,
linux-kernel@...r.kernel.org, Lars Persson <larper@...s.com>
Subject: [PATCH 1/2] clk: add device tree binding for artpec-6 pll1 clock
Add device tree documentation for the main PLL in the Artpec-6 SoC.
Signed-off-by: Lars Persson <larper@...s.com>
---
Documentation/devicetree/bindings/clock/artpec6.txt | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/artpec6.txt
diff --git a/Documentation/devicetree/bindings/clock/artpec6.txt b/Documentation/devicetree/bindings/clock/artpec6.txt
new file mode 100644
index 0000000..521fec8
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/artpec6.txt
@@ -0,0 +1,16 @@
+* Clock bindings for Axis ARTPEC-6 chip
+
+Required properties:
+- #clock-cells: Should be <0>
+- compatible: Should be "axis,artpec6-pll1-clock"
+- reg: Address and length of the DEVSTAT register.
+- clocks: The PLL's input clock.
+
+Examples:
+
+pll1_clk: pll1_clk {
+ #clock-cells = <0>;
+ compatible = "axis,artpec6-pll1-clock";
+ reg = <0xf8000000 4>;
+ clocks = <&ext_clk>;
+};
--
2.1.4
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