linux-kernel - Re: [PATCH 3/3] ARM64: zynqmp: Use 64bit size cell format

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:	Thu, 11 Feb 2016 13:49:58 -0600
From:	Rob Herring <robh+dt@...nel.org>
To:	Michal Simek <monstr@...str.eu>
Cc:	Michal Simek <michal.simek@...inx.com>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>,
	Sören Brinkmann <soren.brinkmann@...inx.com>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	Suneel Garapati <suneel.garapati@...inx.com>,
	Arnd Bergmann <arnd@...db.de>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	Kumar Gala <galak@...eaurora.org>,
	Ian Campbell <ijc+devicetree@...lion.org.uk>,
	Shubhrajyoti Datta <shubhraj@...inx.com>,
	Pawel Moll <pawel.moll@....com>,
	Will Deacon <will.deacon@....com>,
	Catalin Marinas <catalin.marinas@....com>,
	Mark Rutland <mark.rutland@....com>
Subject: Re: [PATCH 3/3] ARM64: zynqmp: Use 64bit size cell format

On Thu, Feb 11, 2016 at 12:58 PM, Michal Simek <monstr@...str.eu> wrote:
> Hi Rob,
>
> On 11.2.2016 17:13, Rob Herring wrote:
>> On Thu, Feb 11, 2016 at 6:26 AM, Michal Simek <michal.simek@...inx.com> wrote:
>>> Use 64bit size cell format instead of 32bit for memory
>>> description. Change 64bit sizes also for all others IPs.
>>
>> Why? As is, this change is completely pointless because nothing needs
>> a >4GB size. Do you have peripherals with >4GB size?
>
> The change I need to do is to support more than 4GB memory. Memory space
> is divided to some parts. 2GB connected to hard part below 4GB. There
> there is 1GB connected to PL part below. Then 32GB hard part above of
> 4GB and a lot of space for PL part (~230GB).
>
> PCIe can also address more than 256GB.

So I would expect some amount of the bus structure to be reflected in
the DT. For example, hard and PL IP are probably in separate address
ranges. I'd guess PL bus has additional logic to enable/disable it for
reprogramming, so you'd need a different bus node anyway. For PCIe,
it's probably its own bus too.

> That's why I stand before decision. Change size-cell for all IPs which
> are currently listed. Or just change it for memory node which is listed
> in mainline.
> I am not quite sure how PCIe description will look like and if there is
> any other IP which will required on current buses use sizes more that
> 4GB. That's why I have change all sizes to support more than 4GB.
>
> But definitely current need is to support more than 4GB memory size and
> I have no problem to use not empty ranges property and keep there
> #size-cells = <1>;

Then why aren't you adding to the memory? (the bootloader sets the
actual size is a valid answer)

> Both solution works for me. Definitely thank you for your comments.

Either way, I'd change this when you actually need the change, not by itself.

Rob