linux-kernel - Re: [PATCH v16 0/6] Device Tree support for FPGA programming

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:	Thu, 11 Feb 2016 16:17:13 -0600
From:	atull <atull@...nsource.altera.com>
To:	Rob Herring <robh+dt@...nel.org>
CC:	Pantelis Antoniou <pantelis.antoniou@...sulko.com>,
	Moritz Fischer <moritz.fischer@...us.com>,
	Josh Cartwright <joshc@...com>,
	"Greg Kroah-Hartman" <gregkh@...uxfoundation.org>,
	Michal Simek <monstr@...str.eu>,
	Michal Simek <michal.simek@...inx.com>,
	Pawel Moll <pawel.moll@....com>,
	"Mark Rutland" <mark.rutland@....com>,
	Ian Campbell <ijc+devicetree@...lion.org.uk>,
	Kumar Gala <galak@...eaurora.org>,
	Jonathan Corbet <corbet@....net>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	"linux-doc@...r.kernel.org" <linux-doc@...r.kernel.org>,
	<delicious.quinoa@...il.com>,
	Dinh Nguyen <dinguyen@...nsource.altera.com>
Subject: Re: [PATCH v16 0/6] Device Tree support for FPGA programming

On Thu, 11 Feb 2016, atull wrote:

> On Thu, 11 Feb 2016, Rob Herring wrote:
> 
> > On Thu, Feb 11, 2016 at 2:49 PM, atull <atull@...nsource.altera.com> wrote:
> > > On Fri, 5 Feb 2016, atull@...nsource.altera.com wrote:
> > >
> > >> From: Alan Tull <atull@...nsource.altera.com>
> > >>
> > >> v16 Refactors the FPGA Area and FPGA Bus into single thing called an
> > >> FPGA Region and eliminates using simple-bus.  I'm using the word
> > >> "region" as it's a term is used in the literature of both the major
> > >> FPGA manufacturors.
> > >>
> > >> Changes for v16:
> > >> * Refactor the FPGA Area and FPGA Bus into a FPGA Region.
> > >> * Don't use simple-bus.
> > >> * FPGA Managers and FPGA Bridges are now specified by phandle using the
> > >>   "fpga-mgr" and "fpga-bridges" properties.  fpga-bridges can specify
> > >>   more than one bridge.
> > >> * Device Tree overlays should be targeted to a FPGA Region.
> > >> * The overlays need only contain firmware-name and the child nodes.
> > >> * To model a system containing >1 partial reconfiguration region,
> > >>   an overlay could add FPGA Regions to the base FPGA Regions.
> > >> * Child FPGA Regions inherit the parent FGPA Manager, but specify
> > >>   their own set of bridges if needes as partial reconfig regions
> > >>   will likely need their own bridges.
> > >> * All this is discussed in bindings/fpga/fpga-region.txt
> > >>
> > >> One other highlight:
> > >> The little engine that runs this thing is a reconfig notifier
> > >> in fpga-region.c.  This notifier that will program an FPGA if a
> > >> "firmware-name" property gets added to a fpga-region.  Then
> > >> it will call of_platform_populate().  The current behavior in Linux
> > >> when a DT overlay is applied is that the reconfig notifications
> > >> go out in heirarchical order: first notifications are for the
> > >> properties, then notifications for the child nodes.  So an overlay
> > >> that adds a 'firmware-name' property and some child nodes to a
> > >> fpga-region will cause FPGA programming and child node
> > >> populating in the right order.
> > >
> > > I figured out how to get rid of the reconfig notifier.
> > >
> > >>
> > >> One issue with the dynamic DT stuff:
> > >> I've tried returning and error from the notifier if FPGA programming
> > >> fails; the error is noted on the console, but the child nodes
> > >> get probed anyway.
> > >
> > > I looked into it further and now I've got a solution for this issue
> > > that I can post soon.  I can stop using the DT overlay configfs
> > > interface and add a sysfs file for applying an overlay to an FPGA
> > > region.  The FPGA region implementation will see the overlay before it
> > > becomes part of the live tree.  Then it can do the FPGA programming
> > > and see that succeed before the child nodes become part of the live
> > > tree.  If FPGA programming fails, the overlay will be rejected before
> > > it becomes part of the live tree.  By the time 'firmware-name' and the
> > > child nodes show up in the live tree, they will be post-configuration
> > > information.
> > 
> > Um, no. We don't need 2 interfaces for loading overlays from
> > userspace. I could see this being a common problem and it needs to be
> > solved. But given the configfs interface is not upstream yet, perhaps
> > you should worry about that after the current series is in.
> > 
> > Perhaps we need a pre-add notifier and the core will only load the
> > overlay if nothing handles it. Really, a solution without notifiers
> > would be preferred. Maybe register handlers with the DT core for
> > certain paths.
> > 
> > Rob
> > 
> 
> Yes.  If any handler returns error, the overlay doesn't go into the
> main tree.  Handler type to be registed could be:
> 
>   int pre_add_handler(struct device_node *overlay,
>                       struct device_node *target)

And a third parameter of some flags to indicate whether the
overlay is being added or removed.

> 
> That gives us the overlay after it's been unflattened and phandles
> resolved and the node that it was targeted to.  I was going to
> need find_target_node() to be exported, but this avoids that.
> 
> Registration could by compatible string, of match, or path.  Path
> would be too rigid in my case, I'd want to register for compatible
> "fpga-region"
> 
> Alan
>