linux-kernel - Re: [PATCH V3 2/4] gpio: gpio-f81504: Add Fintek F81504/508/512 PCIE-to-UART/GPIO GPIOLIB support

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Message-ID: <CACRpkdYODcp5P7QT1b-9HNjA1j4X_UAVs+AfCgjfgpjAA2PnWQ@mail.gmail.com>
Date:	Tue, 16 Feb 2016 16:22:41 +0100
From:	Linus Walleij <linus.walleij@...aro.org>
To:	Peter Hung <hpeter@...il.com>
Cc:	Alexandre Courbot <gnurou@...il.com>,
	Greg KH <gregkh@...uxfoundation.org>,
	Andy Shevchenko <andriy.shevchenko@...ux.intel.com>,
	Paul Gortmaker <paul.gortmaker@...driver.com>,
	Lee Jones <lee.jones@...aro.org>, Jiri Slaby <jslaby@...e.com>,
	One Thousand Gnomes <gnomes@...rguk.ukuu.org.uk>,
	Peter H <peter_hong@...tek.com.tw>,
	Heikki Krogerus <heikki.krogerus@...ux.intel.com>,
	Peter Hurley <peter@...leysoftware.com>,
	Soeren Grunewald <soeren.grunewald@...y.de>,
	Wang YanQing <udknight@...il.com>,
	Adam Lee <adam.lee@...onical.com>,
	Arnd Bergmann <arnd@...db.de>,
	Joachim Eastwood <manabian@...il.com>,
	Scott Wood <scottwood@...escale.com>,
	Masahiro Yamada <yamada.masahiro@...ionext.com>,
	Paul Burton <paul.burton@...tec.com>,
	Måns Rullgård <mans@...sr.com>,
	Matthias Brugger <matthias.bgg@...il.com>,
	Ralf Baechle <ralf@...ux-mips.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"linux-gpio@...r.kernel.org" <linux-gpio@...r.kernel.org>,
	"linux-serial@...r.kernel.org" <linux-serial@...r.kernel.org>,
	tom_tsai@...tek.com.tw, Peter Hung <hpeter+linux_kernel@...il.com>
Subject: Re: [PATCH V3 2/4] gpio: gpio-f81504: Add Fintek F81504/508/512
 PCIE-to-UART/GPIO GPIOLIB support

On Tue, Feb 16, 2016 at 7:55 AM, Peter Hung <hpeter@...il.com> wrote:

> This driver is GPIOLIB driver for F81504/508/512, it'll handle the
> GPIOLIB operation of this device. This module will depend on
> MFD_FINTEK_F81504_CORE.
>
> IC function list:
>     F81504: Max 2x8 GPIOs and max 4 serial ports
>         port2/3 are multi-function
>     F81508: Max 6x8 GPIOs and max 8 serial ports
>         port2/3 are multi-function, port8/9/10/11 are gpio only
>     F81512: Max 6x8 GPIOs and max 12 serial ports
>         port2/3/8/9/10/11 are multi-function
>
> GPIO register:
> PCI Configuration space:
>     F0h: bit0~5: Enable GPIO0~5
>          bit6~7: Reserve
>     F3h: bit0~5: Multi-Functional Flag (0:GPIO/1:UART)
>          bit0: UART2 pin out for UART2 / GPIO0
>          bit1: UART3 pin out for UART3 / GPIO1
>          bit2: UART8 pin out for UART8 / GPIO2
>          bit3: UART9 pin out for UART9 / GPIO3
>          bit4: UART10 pin out for UART10 / GPIO4
>          bit5: UART11 pin out for UART11 / GPIO5
>          bit6~7: Reserve
>     F1h: IO address (LSB)
>     F2h: IO address (MSB)
>     F8h + 8 * set: Direction control (bitwise)
>          bitx: 0 - Input mode
>          bitx: 1 - Output mode
>     F9h + 8 * set: Drive ability control (bitwise)
>          bitx: 0 - Open drain (default)
>          bitx: 1 - Push Pull
>          In this driver, we only implements open drain mode.
>
> IO space:
>     (IO base + 0~5): GPIO-0x~5x in/out value (bitwise)
>
> Suggested-by: One Thousand Gnomes <gnomes@...rguk.ukuu.org.uk>
> Suggested-by: Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
> Signed-off-by: Peter Hung <hpeter+linux_kernel@...il.com>

Acked-by: Linus Walleij <linus.walleij@...aro.org>

It's fine with me if this is queued in MFD, serial or whatever tree, or
we can wait until the MFD parts are in and take it for the next merge
window.

Yours,
Linus Walleij