[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <1455757572-44955-6-git-send-email-qiang.zhao@nxp.com>
Date: Thu, 18 Feb 2016 09:06:11 +0800
From: Zhao Qiang <qiang.zhao@....com>
To: <robh+dt@...nel.org>
CC: <oss@...error.net>, <leoyang.li@....com>,
<linux-kernel@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linuxppc-dev@...ts.ozlabs.org>, Zhao Qiang <qiang.zhao@....com>
Subject: [PATCH v2 6/7] T104xRDB: Add qe node to t104xrdb
add qe node to t104xrdb.dtsi
Signed-off-by: Zhao Qiang <qiang.zhao@....com>
---
Changes for v2
- rebase
arch/powerpc/boot/dts/fsl/t104xrdb.dtsi | 40 +++++++++++++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/arch/powerpc/boot/dts/fsl/t104xrdb.dtsi b/arch/powerpc/boot/dts/fsl/t104xrdb.dtsi
index 830ea48..3b08601 100644
--- a/arch/powerpc/boot/dts/fsl/t104xrdb.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t104xrdb.dtsi
@@ -186,4 +186,44 @@
0 0x00010000>;
};
};
+
+ qe: qe@...140000 {
+ ranges = <0x0 0xf 0xfe140000 0x40000>;
+ reg = <0xf 0xfe140000 0 0x480>;
+ brg-frequency = <0>;
+ bus-frequency = <0>;
+
+ si1: si@700 {
+ compatible = "fsl,qe-si";
+ reg = <0x700 0x80>;
+ };
+
+ siram1: siram@...0 {
+ compatible = "fsl,qe-siram";
+ reg = <0x1000 0x800>;
+ };
+
+ ucc_hdlc: ucc@...0 {
+ compatible = "fsl,ucc-hdlc";
+ rx-clock-name = "clk8";
+ tx-clock-name = "clk9";
+ fsl,rx-sync-clock = "rsync_pin";
+ fsl,tx-sync-clock = "tsync_pin";
+ fsl,tx-timeslot = <0xfffffffe>;
+ fsl,rx-timeslot = <0xfffffffe>;
+ fsl,tdm-framer-type = "e1";
+ fsl,tdm-mode = "normal";
+ fsl,tdm-id = <0>;
+ fsl,siram-entry-id = <0>;
+ fsl,tdm-interface;
+ };
+
+ ucc_serial: ucc@...0 {
+ device_type = "serial";
+ compatible = "ucc_uart";
+ port-number = <1>;
+ rx-clock-name = "brg2";
+ tx-clock-name = "brg2";
+ };
+ };
};
--
2.1.0.27.g96db324
Powered by blists - more mailing lists