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Date:	Thu, 18 Feb 2016 08:35:48 -0600
From:	Rob Herring <robh@...nel.org>
To:	Andre Przywara <andre.przywara@....com>
Cc:	Maxime Ripard <maxime.ripard@...e-electrons.com>,
	Chen-Yu Tsai <wens@...e.org>, linux-sunxi@...glegroups.com,
	Arnd Bergmann <arnd@...db.de>,
	linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
	Emilio López <emilio@...pez.com.ar>,
	Michael Turquette <mturquette@...libre.com>,
	Stephen Boyd <sboyd@...eaurora.org>, linux-clk@...r.kernel.org,
	Jens Kuske <jenskuske@...il.com>,
	Pawel Moll <pawel.moll@....com>,
	Mark Rutland <mark.rutland@....com>,
	Ian Campbell <ijc+devicetree@...lion.org.uk>,
	Kumar Gala <galak@...eaurora.org>, devicetree@...r.kernel.org
Subject: Re: [PATCH v2 3/8] DT: clk: sunxi: add binding doc for the
 multi-bus-gates clock

On Wed, Feb 17, 2016 at 11:43:55AM +0000, Andre Przywara wrote:
> Recent Allwinner SoCs introduced a bus gates clock which can have
> different parents for individual gates.
> For the time being we encoded this relation in the driver.
> This commit specifies a new binding which allows to encode this in
> the DT by using a child node for each parent clock used. This allows
> to specify any kind of relation efficiently and also keeps the very
> same kernel driver for all SoCs at the same time.
> 
> Signed-off-by: Andre Przywara <andre.przywara@....com>
> ---
>  Documentation/devicetree/bindings/clock/sunxi.txt | 6 ++++++
>  1 file changed, 6 insertions(+)

Whether this makes sense or not for sunxi, I don't know. But for the 
binding:

Acked-by: Rob Herring <robh@...nel.org>


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