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Message-ID: <56C61433.2090006@caviumnetworks.com> Date: Thu, 18 Feb 2016 10:57:55 -0800 From: David Daney <ddaney@...iumnetworks.com> To: Will Deacon <will.deacon@....com>, "Pinski, Andrew" <Andrew.Pinski@...iumnetworks.com> CC: Jan Glauber <jglauber@...ium.com>, Mark Rutland <mark.rutland@....com>, <linux-kernel@...r.kernel.org>, <linux-arm-kernel@...ts.infradead.org> Subject: Re: [PATCH v4 4/5] arm64/perf: Enable PMCR long cycle counter bit On 02/18/2016 09:34 AM, Will Deacon wrote: > On Thu, Feb 18, 2016 at 05:50:13PM +0100, Jan Glauber wrote: >> With the long cycle counter bit (LC) disabled the cycle counter is not >> working on ThunderX SOC (ThunderX only implements Aarch64). >> Also, according to documentation LC == 0 is deprecated. >> >> To keep the code simple the patch does not introduce 64 bit wide counter >> functions. Instead writing the cycle counter always sets the upper >> 32 bits so overflow interrupts are generated as before. >> >> Original patch from Andrew Pinksi <Andrew.Pinksi@...iumnetworks.com> > > What does this mean? Do we need Andrew's S-o-B, or is this a fresh patch? I don't believe we need Andrew's S-o-B as the assertion of the Developer's Certificate of Origin 1.1 clauses (a), (b) and (d) is being made. Specifically, clause (c) does not apply. However this may be a gray area, so we could put on Andrew's S-o-B if that would make everybody happier. David Daney > > Will > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@...ts.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel >
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