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Message-ID: <20160222214700.GV4847@codeaurora.org>
Date: Mon, 22 Feb 2016 13:47:00 -0800
From: Stephen Boyd <sboyd@...eaurora.org>
To: dinguyen@...nsource.altera.com
Cc: dinh.linux@...il.com, mturquette@...libre.com,
mgerlach@...nsource.altera.com, linux-clk@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH] clk: socfpga: allow for multiple parents on Arria10
periph clocks
On 02/22, dinguyen@...nsource.altera.com wrote:
> From: Dinh Nguyen <dinguyen@...nsource.altera.com>
>
> There are some Arria10 clocks of type "altr,socfpga-a10-perip-clk" that can
> have multiple parents. Fix up the __socfpga_periph_init() to call
> of_clk_parent_fill() that will return the appropriate number of parents.
>
> Also, update __socfpga_gate_init() to call of_clk_parent_fill() helper
> function.
>
> Signed-off-by: Dinh Nguyen <dinguyen@...nsource.altera.com>
> ---
Applied to clk-next
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