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Message-ID: <1456236764-1569-2-git-send-email-Suravee.Suthikulpanit@amd.com>
Date: Tue, 23 Feb 2016 08:12:35 -0600
From: Suravee Suthikulpanit <Suravee.Suthikulpanit@....com>
To: <joro@...tes.org>, <bp@...en8.de>, <peterz@...radead.org>,
<mingo@...hat.com>, <acme@...nel.org>
CC: <andihartmann@...enet.de>, <vw@...mu.org>, <labbott@...hat.com>,
<linux-kernel@...r.kernel.org>, <iommu@...ts.linux-foundation.org>,
"Suravee Suthikulpanit" <Suravee.Suthikulpanit@....com>,
Suravee Suthikulpanit <suravee.suthikulpanit@....com>
Subject: [PATCH V5 01/10] perf/amd/iommu: Misc fix up perf_iommu_read
This patch contains the follow minor fixup:
* Fixed overflow handling since u64 delta would lose the MSB sign bit.
* Remove unnecessary local64_set().
* Coding style and make use of GENMASK_ULL macro.
Cc: Peter Zijlstra <peterz@...radead.org>
Cc: Borislav Petkov <bp@...en8.de>
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@....com>
---
arch/x86/events/amd/iommu.c | 23 ++++++++++++-----------
1 file changed, 12 insertions(+), 11 deletions(-)
diff --git a/arch/x86/events/amd/iommu.c b/arch/x86/events/amd/iommu.c
index 629bc70..9da0d16 100644
--- a/arch/x86/events/amd/iommu.c
+++ b/arch/x86/events/amd/iommu.c
@@ -314,9 +314,8 @@ static void perf_iommu_start(struct perf_event *event, int flags)
static void perf_iommu_read(struct perf_event *event)
{
- u64 count = 0ULL;
- u64 prev_raw_count = 0ULL;
- u64 delta = 0ULL;
+ u64 cnt, prev;
+ s64 delta;
struct hw_perf_event *hwc = &event->hw;
pr_debug("perf: amd_iommu:perf_iommu_read\n");
@@ -325,18 +324,20 @@ static void perf_iommu_read(struct perf_event *event)
IOMMU_PC_COUNTER_REG, &count, false);
/* IOMMU pc counter register is only 48 bits */
- count &= 0xFFFFFFFFFFFFULL;
+ cnt &= GENMASK_ULL(48, 0);
- prev_raw_count = local64_read(&hwc->prev_count);
- if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
- count) != prev_raw_count)
- return;
+ prev = local64_read(&hwc->prev_count);
- /* Handling 48-bit counter overflowing */
- delta = (count << COUNTER_SHIFT) - (prev_raw_count << COUNTER_SHIFT);
+ /*
+ * Since we do not enable counter overflow interrupts,
+ * we do not have to worry about prev_count changing on us.
+ */
+ local64_set(&hwc->prev_count, cnt);
+
+ /* Handle 48-bit counter overflow */
+ delta = (cnt << COUNTER_SHIFT) - (prev << COUNTER_SHIFT);
delta >>= COUNTER_SHIFT;
local64_add(delta, &event->count);
-
}
static void perf_iommu_stop(struct perf_event *event, int flags)
--
1.9.1
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