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Message-ID: <CAHz2CGVSJDdTKkBfoczd51A6+xQML5RzVc2BmbRBgoNntXXmyg@mail.gmail.com>
Date: Thu, 25 Feb 2016 14:41:07 +0800
From: Jianyu Zhan <nasa4836@...il.com>
To: Paul McKenney <paulmck@...ux.vnet.ibm.com>
Cc: Mathieu Desnoyers <mathieu.desnoyers@...icios.com>,
LKML <linux-kernel@...r.kernel.org>,
Ingo Molnar <mingo@...nel.org>,
Lai Jiangshan <jiangshanlai@...il.com>, dipankar@...ibm.com,
Andrew Morton <akpm@...ux-foundation.org>,
josh@...htriplett.org, Thomas Gleixner <tglx@...utronix.de>,
Peter Zijlstra <peterz@...radead.org>,
rostedt <rostedt@...dmis.org>,
David Howells <dhowells@...hat.com>,
Eric Dumazet <edumazet@...gle.com>, dvhart@...ux.intel.com,
fweisbec@...il.com, Oleg Nesterov <oleg@...hat.com>,
bobby prani <bobby.prani@...il.com>
Subject: Re: [PATCH tip/core/rcu 02/14] documentation: Fix control dependency
and identical stores
On Thu, Feb 25, 2016 at 5:40 AM, Paul E. McKenney
<paulmck@...ux.vnet.ibm.com> wrote:
> So ordering between the read from "a" and the write to "b" is still
> preserved. The reason this works is that the smp_mb() does all the
> ordering, so the fact that the control dependency has been eliminated
> is irrelevant.
Thanks, Paul, nice clarification.
I thinks this example qualifies as an good example to demonstrate the subtle
scope of effect of these two level barriers.
A vivid example is always better for understanding instead of learning
"barrier() is compiler-level
barrier, and smp_*mb() is processor-level barrier" by rote ,
especially for the new comers to memory-barriers.txt. ;-)
Thanks,
Jianyu Zhan
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