linux-kernel - [tip:irq/core] irqchip/mips-gic: Add new DT property to reserve IPIs

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Message-ID: <tip-16a8083cedbe628228dbb08fc1469c70e6208619@git.kernel.org>
Date:	Thu, 25 Feb 2016 02:06:16 -0800
From:	tip-bot for Qais Yousef <tipbot@...or.com>
To:	linux-tip-commits@...r.kernel.org
Cc:	jason@...edaemon.net, tglx@...utronix.de, ralf@...ux-mips.org,
	jiang.liu@...ux.intel.com, lisa.parratt@...tec.com,
	marc.zyngier@....com, robh@...nel.org, mingo@...nel.org,
	hpa@...or.com, linux-kernel@...r.kernel.org, qsyousef@...il.com,
	qais.yousef@...tec.com, linux-mips@...ux-mips.org
Subject: [tip:irq/core] irqchip/mips-gic: Add new DT property to reserve
 IPIs

Commit-ID:  16a8083cedbe628228dbb08fc1469c70e6208619
Gitweb:     http://git.kernel.org/tip/16a8083cedbe628228dbb08fc1469c70e6208619
Author:     Qais Yousef <qais.yousef@...tec.com>
AuthorDate: Tue, 8 Dec 2015 13:20:30 +0000
Committer:  Thomas Gleixner <tglx@...utronix.de>
CommitDate: Thu, 25 Feb 2016 10:56:58 +0100

irqchip/mips-gic: Add new DT property to reserve IPIs

The new property will allow to specify the range of GIC hwirqs to use for IPIs.

This is an optinal property. We preserve the previous behaviour of allocating
the last 2 * gic_vpes if it's not specified or DT is not supported.

Signed-off-by: Qais Yousef <qais.yousef@...tec.com>
Acked-by: Rob Herring <robh@...nel.org>
Acked-by: Ralf Baechle <ralf@...ux-mips.org>
Cc: <jason@...edaemon.net>
Cc: <marc.zyngier@....com>
Cc: <jiang.liu@...ux.intel.com>
Cc: <linux-mips@...ux-mips.org>
Cc: <lisa.parratt@...tec.com>
Cc: Qais Yousef <qsyousef@...il.com>
Link: http://lkml.kernel.org/r/1449580830-23652-20-git-send-email-qais.yousef@imgtec.com
Signed-off-by: Thomas Gleixner <tglx@...utronix.de>
---
 .../devicetree/bindings/interrupt-controller/mips-gic.txt    |  7 +++++++
 drivers/irqchip/irq-mips-gic.c                               | 12 ++++++++++--
 2 files changed, 17 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt b/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt
index aae4c38..1735953 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt
@@ -23,6 +23,12 @@ Optional properties:
 - mti,reserved-cpu-vectors : Specifies the list of CPU interrupt vectors
   to which the GIC may not route interrupts.  Valid values are 2 - 7.
   This property is ignored if the CPU is started in EIC mode.
+- mti,reserved-ipi-vectors : Specifies the range of GIC interrupts that are
+  reserved for IPIs.
+  It accepts 2 values, the 1st is the starting interrupt and the 2nd is the size
+  of the reserved range.
+  If not specified, the driver will allocate the last 2 * number of VPEs in the
+  system.
 
 Required properties for timer sub-node:
 - compatible : Should be "mti,gic-timer".
@@ -44,6 +50,7 @@ Example:
 		#interrupt-cells = <3>;
 
 		mti,reserved-cpu-vectors = <7>;
+		mti,reserved-ipi-vectors = <40 8>;
 
 		timer {
 			compatible = "mti,gic-timer";
diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c
index 37831a5..94a30da 100644
--- a/drivers/irqchip/irq-mips-gic.c
+++ b/drivers/irqchip/irq-mips-gic.c
@@ -957,6 +957,7 @@ static void __init __gic_init(unsigned long gic_base_addr,
 			      struct device_node *node)
 {
 	unsigned int gicconfig;
+	unsigned int v[2];
 
 	__gic_base_addr = gic_base_addr;
 
@@ -1027,8 +1028,15 @@ static void __init __gic_init(unsigned long gic_base_addr,
 
 	gic_ipi_domain->bus_token = DOMAIN_BUS_IPI;
 
-	/* Make the last 2 * gic_vpes available for IPIs */
-	bitmap_set(ipi_resrv, gic_shared_intrs - 2 * gic_vpes, 2 * gic_vpes);
+	if (node &&
+	    !of_property_read_u32_array(node, "mti,reserved-ipi-vectors", v, 2)) {
+		bitmap_set(ipi_resrv, v[0], v[1]);
+	} else {
+		/* Make the last 2 * gic_vpes available for IPIs */
+		bitmap_set(ipi_resrv,
+			   gic_shared_intrs - 2 * gic_vpes,
+			   2 * gic_vpes);
+	}
 
 	gic_basic_init();
 }