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Date: Fri, 26 Feb 2016 23:09:42 +0100 From: Andrew Lunn <andrew@...n.ch> To: Vivien Didelot <vivien.didelot@...oirfairelinux.com> Cc: Kevin Smith <kevin.smith@...csyscorp.com>, "netdev@...r.kernel.org" <netdev@...r.kernel.org>, "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>, "kernel@...oirfairelinux.com" <kernel@...oirfairelinux.com>, "David S. Miller" <davem@...emloft.net>, Florian Fainelli <f.fainelli@...il.com>, Sergei Shtylyov <sergei.shtylyov@...entembedded.com>, Guenter Roeck <linux@...ck-us.net>, Neil Armstrong <narmstrong@...libre.com>, Sascha Hauer <s.hauer@...gutronix.de>, Russell King <rmk+kernel@....linux.org.uk> Subject: Re: [PATCH net-next 7/9] net: dsa: mv88e6xxx: restore VLANTable map control On Fri, Feb 26, 2016 at 04:37:39PM -0500, Vivien Didelot wrote: > Hi Kevin, Andrew, > > Andrew Lunn <andrew@...n.ch> writes: > > > On Fri, Feb 26, 2016 at 08:45:28PM +0000, Kevin Smith wrote: > >> Hi Vivien, > >> > >> On 02/26/2016 12:16 PM, Vivien Didelot wrote: > >> > + /* allow CPU port or DSA link(s) to send frames to every port */ > >> > + if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) { > >> > + output_ports = mask; > >> > + } else { > > > >> Is this always correct? Are there situations where a CPU or neighboring > >> switch should not be allowed to access another port? (e.g. Figure 6 or 7 > >> in the 88E6352 functional specification). > > Given Linux expectations (described below by Andrew) I'd say yes, this > is always correct. But I'd be curious to know if someone has counter > examples for this. > > > What do these figures show? > > The figure shows the following VLANTable config: > > Port 0 1 2 3 4 5 6 > 0 - * * * - - * > 1 * - * * - - * > 2 * * - * - - * > 3 * * * - - - * > 4 - - - - - * - > 5 - - - - * - - > 6 * * * * - - - > > There is two independant groups: 0, 1, 2, 3, 6 (LAN, 6 is CPU/Router), > and 4, 5 (4 is WAN and 5 is CPU/Router): Ah, two CPU interfaces. We don't support that yet. I do have patches, but i took a different approach. They just load balance, by some definition of 'load balance' between the two CPU ports. Andrew
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