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Message-ID: <CAGb2v66P5zKkbriUOnvg9ms-HSpmYDQ7RtQ5MG9fLopo3pwPoQ@mail.gmail.com>
Date: Sun, 28 Feb 2016 20:09:48 -0800
From: Chen-Yu Tsai <wens@...e.org>
To: Vishnu Patekar <vishnupatekar0510@...il.com>
Cc: Rob Herring <robh+dt@...nel.org>, Jonathan Corbet <corbet@....net>,
Pawel Moll <pawel.moll@....com>,
Mark Rutland <mark.rutland@....com>,
Ian Campbell <ijc+devicetree@...lion.org.uk>,
Kumar Gala <galak@...eaurora.org>,
Maxime Ripard <maxime.ripard@...e-electrons.com>,
Russell King - ARM Linux <linux@....linux.org.uk>,
Emilio Lopez <emilio@...pez.com.ar>,
Jens Kuske <jenskuske@...il.com>,
Hans De Goede <hdegoede@...hat.com>,
Chen-Yu Tsai <wens@...e.org>,
devicetree <devicetree@...r.kernel.org>,
linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>,
linux-kernel <linux-kernel@...r.kernel.org>,
linux-sunxi <linux-sunxi@...glegroups.com>,
"linux-gpio@...r.kernel.org" <linux-gpio@...r.kernel.org>,
Linus Walleij <linus.walleij@...aro.org>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...eaurora.org>,
Reinder de Haan <patchesrdh@...as.com>,
linux-clk <linux-clk@...r.kernel.org>
Subject: Re: [PATCH v2 02/13] clk: sunxi: add ahb1 clock for A83T
Hi,
On Sun, Feb 28, 2016 at 7:18 AM, Vishnu Patekar
<vishnupatekar0510@...il.com> wrote:
> AHB1 on A83T is similar to ahb1 on A31, except parents are different.
> clock index 0b1x is PLL6.
>
> Signed-off-by: Vishnu Patekar <vishnupatekar0510@...il.com>
> Acked-by: Chen-Yu Tsai <wens@...e.org>
> Acked-by: Rob Herring <robh@...nel.org>
> ---
> Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
> drivers/clk/sunxi/clk-sunxi.c | 76 +++++++++++++++++++++++
> 2 files changed, 77 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
> index c09f59b..2ee7841 100644
> --- a/Documentation/devicetree/bindings/clock/sunxi.txt
> +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
> @@ -29,6 +29,7 @@ Required properties:
> "allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31
> "allwinner,sun9i-a80-cpus-clk" - for the CPUS on A80
> "allwinner,sun6i-a31-ahb1-clk" - for the AHB1 clock on A31
> + "allwinner,sun8i-a83t-ahb1-clk" - for the AHB1 clock on A83T
> "allwinner,sun8i-h3-ahb2-clk" - for the AHB2 clock on H3
> "allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
> "allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23
> diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
> index 99f60ef..0ae1f09 100644
> --- a/drivers/clk/sunxi/clk-sunxi.c
> +++ b/drivers/clk/sunxi/clk-sunxi.c
> @@ -344,6 +344,67 @@ static void sun6i_ahb1_recalc(struct factors_request *req)
> req->rate >>= req->p;
> }
>
> +#define SUN8I_A83T_AHB1_PARENT_PLL6 2
> +/**
> + * sun8i_a83t_get_ahb_factors() - calculates m, p factors for AHB
> + * AHB rate is calculated as follows
> + * rate = parent_rate >> p
> + *
> + * if parent is pll6, then
> + * parent_rate = pll6 rate / (m + 1)
> + */
> +
> +static void sun8i_a83t_get_ahb1_factors(struct factors_request *req)
> +{
> + u8 div, calcp, calcm = 1;
> +
> + /*
> + * clock can only divide, so we will never be able to achieve
> + * frequencies higher than the parent frequency
> + */
> + if (req->parent_rate && req->rate > req->parent_rate)
> + req->rate = req->parent_rate;
> +
> + div = DIV_ROUND_UP(req->parent_rate, req->rate);
> +
> + /* calculate pre-divider if parent is pll6 */
> + if (req->parent_index >= SUN8I_A83T_AHB1_PARENT_PLL6) {
> + if (div < 4)
> + calcp = 0;
> + else if (div / 2 < 4)
> + calcp = 1;
> + else if (div / 4 < 4)
> + calcp = 2;
> + else
> + calcp = 3;
> +
> + calcm = DIV_ROUND_UP(div, 1 << calcp);
> + } else {
> + calcp = __roundup_pow_of_two(div);
> + calcp = calcp > 3 ? 3 : calcp;
> +}
Indent here.
> +
> + req->rate = (req->parent_rate / calcm) >> calcp;
> + req->p = calcp;
> + req->m = calcm - 1;
> +}
> +
> +/**
> +* sun8i_a83t_ahb1_recalc() - calculates AHB clock rate from m, p factors and
> +* parent index
Whitespace here.
> +*/
> +static void sun8i_a83t_ahb1_recalc(struct factors_request *req)
> +{
> + req->rate = req->parent_rate;
> +
> +/* apply pre-divider first if parent is pll6 */
Indent here.
ChenYu
> + if (req->parent_index >= SUN6I_AHB1_PARENT_PLL6)
> + req->rate /= req->m + 1;
> +
> + /* clk divider */
> + req->rate >>= req->p;
> +}
> +
> /**
> * sun4i_get_apb1_factors() - calculates m, p factors for APB1
> * APB1 rate is calculated as follows
> @@ -555,6 +616,14 @@ static const struct factors_data sun6i_ahb1_data __initconst = {
> .recalc = sun6i_ahb1_recalc,
> };
>
> +static const struct factors_data sun8i_a83t_ahb1_data __initconst = {
> + .mux = 12,
> + .muxmask = BIT(1) | BIT(0),
> + .table = &sun6i_ahb1_config,
> + .getter = sun8i_a83t_get_ahb1_factors,
> + .recalc = sun8i_a83t_ahb1_recalc,
> +};
> +
> static const struct factors_data sun4i_apb1_data __initconst = {
> .mux = 24,
> .muxmask = BIT(1) | BIT(0),
> @@ -627,6 +696,13 @@ static void __init sun6i_ahb1_clk_setup(struct device_node *node)
> CLK_OF_DECLARE(sun6i_a31_ahb1, "allwinner,sun6i-a31-ahb1-clk",
> sun6i_ahb1_clk_setup);
>
> +static void __init sun8i_a83t_ahb1_clk_setup(struct device_node *node)
> +{
> + sunxi_factors_clk_setup(node, &sun8i_a83t_ahb1_data);
> +}
> +CLK_OF_DECLARE(sun8i_a83t_ahb1, "allwinner,sun8i-a83t-ahb1-clk",
> + sun8i_a83t_ahb1_clk_setup);
> +
> static void __init sun4i_apb1_clk_setup(struct device_node *node)
> {
> sunxi_factors_clk_setup(node, &sun4i_apb1_data);
> --
> 1.9.1
>
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