linux-kernel - Re: [PATCH 1/2] MIPS: Add barriers between dcache & icache flushes

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Message-ID: <20160301022738.GB12741@NP-P-BURTON>
Date:	Tue, 1 Mar 2016 02:27:39 +0000
From:	Paul Burton <paul.burton@...tec.com>
To:	Florian Fainelli <f.fainelli@...il.com>
CC:	<linux-mips@...ux-mips.org>, Ralf Baechle <ralf@...ux-mips.org>,
	"James Hogan" <james.hogan@...tec.com>,
	Joshua Kinard <kumba@...too.org>,
	"Paul Gortmaker" <paul.gortmaker@...driver.com>,
	<linux-kernel@...r.kernel.org>,
	"Maciej W. Rozycki" <macro@...esourcery.com>,
	Markos Chandras <markos.chandras@...tec.com>,
	"Kirill A. Shutemov" <kirill.shutemov@...ux.intel.com>
Subject: Re: [PATCH 1/2] MIPS: Add barriers between dcache & icache flushes

On Mon, Feb 22, 2016 at 04:02:09PM -0800, Florian Fainelli wrote:
> On 22/02/16 10:09, Paul Burton wrote:
> > Index-based cache operations may be arbitrarily reordered by out of
> > order CPUs. Thus code which writes back the dcache & then invalidates
> > the icache using indexed cache ops must include a barrier between
> > operating on the 2 caches in order to prevent the scenario in which:
> > 
> >   - icache invalidation occurs.
> > 
> >   - icache fetch occurs, due to speculation.
> > 
> >   - dcache writeback occurs.
> > 
> > If the above were allowed to happen then the icache would contain stale
> > data. Forcing the dcache writeback to complete before the icache
> > invalidation avoids this.
> 
> Is that also true for CPUs with have cpu_has_ic_fills_dc?

Hi Florian,

Good question. I imagine not, but probably need to think some more & ask
some questions.

Thanks,
    Paul