linux-kernel - Re: [PATCH V2 2/5] EDAC, MCE, AMD: Enable error decoding of Scalable MCA errors

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Message-ID: <20160302105032.GC16954@pd.tnic>
Date:	Wed, 2 Mar 2016 11:50:32 +0100
From:	Borislav Petkov <bp@...en8.de>
To:	Aravind Gopalakrishnan <Aravind.Gopalakrishnan@....com>
Cc:	tony.luck@...el.com, hpa@...or.com, mingo@...hat.com,
	tglx@...utronix.de, dougthompson@...ssion.com,
	mchehab@....samsung.com, x86@...nel.org,
	linux-edac@...r.kernel.org, linux-kernel@...r.kernel.org,
	ashok.raj@...el.com, gong.chen@...ux.intel.com,
	len.brown@...el.com, peterz@...radead.org, ak@...ux.intel.com,
	alexander.shishkin@...ux.intel.com
Subject: Re: [PATCH V2 2/5] EDAC, MCE, AMD: Enable error decoding of Scalable
 MCA errors

On Mon, Feb 29, 2016 at 04:32:56PM -0600, Aravind Gopalakrishnan wrote:
> For Scalable MCA enabled processors, errors are listed
> per IP block. And since it is not required for an IP to
> map to a particular bank, we need to use HWID and McaType
> values from the MCx_IPID register to figure out which IP
> a given bank represents.
> 
> We also have a new bit (TCC) in the MCx_STATUS register
> to indicate Task context is corrupt.
> 
> Add logic here to decode errors from all known IP
> blocks for Fam17h Model 00-0fh and to print TCC errors.
> 
> Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@....com>
> ---
>  arch/x86/include/asm/mce.h           |  53 ++++++
>  arch/x86/kernel/cpu/mcheck/mce_amd.c |  11 ++
>  drivers/edac/mce_amd.c               | 342 ++++++++++++++++++++++++++++++++++-
>  3 files changed, 405 insertions(+), 1 deletion(-)

Ok, applied with a bunch of changes ontop. I'm sending them as a reply
to this message. The second patch is relying on the assumption that a
hwid of 0 is invalid. Is that so?

-- 
Regards/Gruss,
    Boris.

ECO tip #101: Trim your mails when you reply.