linux-kernel - Re: [PATCH v1] watchdog: sama5d4

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Message-ID: <56D8E649.8030500@atmel.com>
Date:	Fri, 4 Mar 2016 09:35:05 +0800
From:	"Yang, Wenyou" <wenyou.yang@...el.com>
To:	Romain Izard <romain.izard.pro@...il.com>,
	<linux-kernel@...r.kernel.org>, <linux-watchdog@...r.kernel.org>,
	<linux-arm-kernel@...ts.infradead.org>,
	Wim Van Sebroeck <wim@...ana.be>
CC:	Guenter Roeck <linux@...ck-us.net>,
	Nicolas Ferre <nicolas.ferre@...el.com>
Subject: Re: [PATCH v1] watchdog: sama5d4_wdt: Reset delay on start

Hi Romain,

On 2016/3/3 18:29, Romain Izard wrote:
> If the internal counter is not refreshed when the watchdog is started
> for the first time, the watchdog will trigger very rapidly. For example,
> opening /dev/watchdog without writing in it will immediately trigger a
> reboot, instead of waiting for the delay to expire.
>
> To avoid this problem, reload the timer on opening the watchdog device.
>
> Command: "while sleep 5; do echo 1; done > /dev/watchdog"
> Before: system reset
> After: the watchdog runs correctly
I didn't reproduce your issue on my side,

run the your commands as follows, it works fine,  the system reset 
doesn't happen.
---8<----
#!/bin/sh

while [ 1 ]
do
         sleep 5;
         echo 1 > /dev/watchdog
done
--->8----

I also check the WDT_MR register before and after enabling watchdog, the 
WDV and WDD fields are correct.

Can you check it again? thank you.

>
> Signed-off-by: Romain Izard <romain.izard.pro@...il.com>
> ---
>   drivers/watchdog/sama5d4_wdt.c | 3 +++
>   1 file changed, 3 insertions(+)
>
> diff --git a/drivers/watchdog/sama5d4_wdt.c b/drivers/watchdog/sama5d4_wdt.c
> index a49634cdc1cc..e162fe140ae1 100644
> --- a/drivers/watchdog/sama5d4_wdt.c
> +++ b/drivers/watchdog/sama5d4_wdt.c
> @@ -15,6 +15,7 @@
>   #include <linux/platform_device.h>
>   #include <linux/reboot.h>
>   #include <linux/watchdog.h>
> +#include <linux/delay.h>
>   
>   #include "at91sam9_wdt.h"
>   
> @@ -58,6 +59,8 @@ static int sama5d4_wdt_start(struct watchdog_device *wdd)
>   	reg = wdt_read(wdt, AT91_WDT_MR);
>   	reg &= ~AT91_WDT_WDDIS;
>   	wdt_write(wdt, AT91_WDT_MR, reg);
> +	udelay(125); /* > 4 cycles at 32,768 Hz */
> +	wdt_write(wdt, AT91_WDT_CR, AT91_WDT_KEY | AT91_WDT_WDRSTT);
>   
>   	return 0;
>   }

Best Regards,
Wenyou Yang