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Message-ID: <CAL1qeaHq2FMPeF9vqPEkpz9v+rcdPoJf2oegZ1afYDL9N6ggKA@mail.gmail.com>
Date: Fri, 4 Mar 2016 13:41:11 -0800
From: Andrew Bresticker <abrestic@...omium.org>
To: Thierry Reding <thierry.reding@...il.com>
Cc: Kishon Vijay Abraham I <kishon@...com>,
Linus Walleij <linus.walleij@...aro.org>,
Stephen Warren <swarren@...dotorg.org>,
Alexandre Courbot <gnurou@...il.com>,
"linux-tegra@...r.kernel.org" <linux-tegra@...r.kernel.org>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"linux-usb@...r.kernel.org" <linux-usb@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
Rob Herring <robh+dt@...nel.org>,
Pawel Moll <pawel.moll@....com>,
Mark Rutland <mark.rutland@....com>,
Ian Campbell <ijc+devicetree@...lion.org.uk>,
Kumar Gala <galak@...eaurora.org>
Subject: Re: [PATCH v10 3/9] dt-bindings: phy: tegra-xusb-padctl: Add Tegra210 support
On Fri, Mar 4, 2016 at 8:19 AM, Thierry Reding <thierry.reding@...il.com> wrote:
> From: Thierry Reding <treding@...dia.com>
>
> Extend the binding to cover the set of feature found in Tegra210.
>
> Signed-off-by: Thierry Reding <treding@...dia.com>
> +PCIe pad:
> +---------
> +
> +Required properties:
> +- clocks: Must contain an entry for each entry in clock-names.
> +- clock-names: Must contain the following entries:
> + - "pll": phandle and specifier referring to the PLLE
> +- resets: Must contain an entry for each entry in reset-names.
> +- reset-names: Must contain the following entries:
> + - "phy": reset for the PCIe UPHY block
> +
> +SATA pad:
> +---------
> +
> +Required properties:
> +- resets: Must contain an entry for each entry in reset-names.
> +- reset-names: Must contain the following entries:
> + - "phy": reset for the SATA UPHY block
Doesn't the SATA pad require PLLE as well? You've included it in the
example DT fragment, but it's absent here.
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