linux-kernel - [PATCH 0/5] x86/RAS: Enable error decoding of AMD Scalable MCA errors

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Message-Id: <1457355741-32651-1-git-send-email-bp@alien8.de>
Date:	Mon,  7 Mar 2016 14:02:16 +0100
From:	Borislav Petkov <bp@...en8.de>
To:	Ingo Molnar <mingo@...nel.org>
Cc:	X86 ML <x86@...nel.org>, linux-edac <linux-edac@...r.kernel.org>,
	LKML <linux-kernel@...r.kernel.org>
Subject: [PATCH 0/5] x86/RAS: Enable error decoding of AMD Scalable MCA errors

From: Borislav Petkov <bp@...e.de>

Hi,

this adds support for the upcoming AMD Scalable MCA error decoding
scheme to Linux (F17h stuff) (patch 2). The rest is cleanups and
clarifications.

Patches ontop of tip/ras/core.

Aravind Gopalakrishnan (5):
  x86/mce: Move MCx_CONFIG MSR definitions
  x86/mce/AMD, EDAC: Enable error decoding of Scalable MCA errors
  x86/mce/AMD: Fix logic to obtain block address
  x86/mce: Clarify comments regarding deferred error
  x86/mce/AMD: Document some functionality

 arch/x86/include/asm/amd_nb.h        |  26 ++-
 arch/x86/include/asm/mce.h           |  69 +++++++-
 arch/x86/include/asm/msr-index.h     |   4 -
 arch/x86/kernel/cpu/mcheck/mce_amd.c | 120 +++++++++----
 drivers/edac/mce_amd.c               | 335 ++++++++++++++++++++++++++++++++++-
 5 files changed, 503 insertions(+), 51 deletions(-)

-- 
2.3.5