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Message-ID: <1457379787-8327-9-git-send-email-tthayer@opensource.altera.com>
Date: Mon, 7 Mar 2016 13:43:04 -0600
From: <tthayer@...nsource.altera.com>
To: <bp@...en8.de>, <dougthompson@...ssion.com>,
<m.chehab@...sung.com>, <robh+dt@...nel.org>, <pawel.moll@....com>,
<mark.rutland@....com>, <ijc+devicetree@...lion.org.uk>,
<galak@...eaurora.org>, <linux@....linux.org.uk>,
<dinguyen@...nsource.altera.com>, <grant.likely@...aro.org>
CC: <devicetree@...r.kernel.org>, <linux-doc@...r.kernel.org>,
<linux-edac@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>, <tthayer.linux@...il.com>,
<tthayer@...nsource.altera.com>
Subject: [PATCHv2 08/11] Documentation: dt: socfpga: Add Altera Arria10 L2 cache binding
From: Thor Thayer <tthayer@...nsource.altera.com>
Add the device tree binding string needed to support the Altera L2
cache on the Arria10 chip.
Signed-off-by: Thor Thayer <tthayer@...nsource.altera.com>
Acked-by: Rob Herring <robh@...nel.org>
---
v2 Correct spelling of Arria10 in patch title.
---
.../bindings/arm/altera/socfpga-eccmgr.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
index 885f93d..4cea386 100644
--- a/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
+++ b/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
@@ -13,7 +13,8 @@ Subcomponents:
L2 Cache ECC
Required Properties:
-- compatible : Should be "altr,socfpga-l2-ecc"
+- compatible : Should be "altr,socfpga-l2-ecc" or
+ "altr,socfpga-a10-l2-ecc"
- reg : Address and size for ECC error interrupt clear registers.
- interrupts : Should be single bit error interrupt, then double bit error
interrupt. Note the rising edge type.
--
1.7.9.5
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