linux-kernel - Re: [PATCH V2] acpi, pci, irq: account for early penalty assignment

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Message-ID: <56DF2258.8020004@codeaurora.org>
Date:	Tue, 8 Mar 2016 14:04:56 -0500
From:	Sinan Kaya <okaya@...eaurora.org>
To:	Bjorn Helgaas <helgaas@...nel.org>
Cc:	linux-acpi@...r.kernel.org, timur@...eaurora.org,
	cov@...eaurora.org, linux-pci@...r.kernel.org,
	ravikanth.nalla@....com, lenb@...nel.org, harish.k@....com,
	ashwin.reghunandanan@....com, bhelgaas@...gle.com,
	rjw@...ysocki.net, linux-kernel@...r.kernel.org,
	Thomas Gleixner <tglx@...utronix.de>
Subject: Re: [PATCH V2] acpi, pci, irq: account for early penalty assignment


>>>> I think there are two issues here that should be teased apart a bit
>>>> more:
>>>>
>>>>   1) Trigger settings: If the IRQ is configured as anything other than
>>>>   level-triggered, active-low, we can't use it at all for a PCI
>>>>   interrupt, and we should return an "infinite" penalty.  We currently
>>>>   increase the penalty for the SCI IRQ if it's not level/low, but
>>>>   doesn't it apply to *all* IRQs, not just the SCI IRQ?
>>>
>>> It makes sense for SCI as it is Intel specific.
>>>
>>> Unfortunately, this cannot be done in an arch independent way. Of course,
>>> ARM had to implement its own thing. While level-triggered, active-low is
>>> good for intel world, it is not for the ARM world. ARM uses active-high
>>> level triggered.
>>
>> I'm confused.  I don't think SCI is Intel-specific.  Per PCI Spec
>> r3.0, sec 2.2.6, PCI interrupts are level-sensitive, asserted low.
>> Per ACPI Spec v3.0, sec 2.1, the SCI is an "active, low, shareable,
>> level interrupt".
>>
>> Are you saying SCI is active-high on ARM?  If so, I don't think that's
>> necessarily a huge problem, although we'd have to audit the ACPI code
>> to make sure we handle it correctly.

We don't have an SCI interrupt on ARM. That's why, I assumed it is an Intel specific
interrupt. However, all legacy interrupts are active-high level sensitive. This is a
limitation of the ARM GIC Interrupt Controller.

Here is what a PCI Link object looks like.

Device(LN0D){
	Name(_HID, EISAID("PNP0C0F")) // PCI interrupt link
	Name(_UID, 4)
	Name(_PRS, ResourceTemplate(){
		Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive, , ,) {123}
	})
	Method(_DIS) {}
	Method(_CRS) { Return (_PRS) }
	Method(_SRS, 1) {}
} 

>>
>> The point here is that a PCI Interrupt Link can only use an IRQ that
>> is level-triggered, active low.  If an IRQ is already set to any other
>> state, whether for an ISA device or for an active-high SCI, we can't
>> use it for a PCI Interrupt Link.

Unfortunately, this still doesn't hold. 

A patch is long overdue for this series. I'll post v3. We can go from there.


-- 
Sinan Kaya
Qualcomm Technologies, Inc. on behalf of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project