linux-kernel - [PATCH v5 5/6] ARM: dts: DRA7: Add TBCLK for PWMSS

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Date:	Mon,  7 Mar 2016 19:23:43 -0600
From:	Franklin S Cooper Jr <fcooper@...com>
To:	thierry.reding@...il.com, robh+dt@...nel.org, pawel.moll@....com,
	mark.rutland@....com, ijc+devicetree@...lion.org.uk,
	galak@...eaurora.org, bcousson@...libre.com, tony@...mide.com,
	linux@....linux.org.uk, paul@...an.com, linux-pwm@...r.kernel.org,
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
	linux-omap@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
	vigneshr@...com
Cc:	Franklin S Cooper Jr <fcooper@...com>
Subject: [PATCH v5 5/6] ARM: dts: DRA7: Add TBCLK for PWMSS

From: Vignesh R <vigneshr@...com>

tbclk is used by ehrpwm to generate PWM waveform on DRA7 SoC. Add Linux
clock to control ehrpwm tbclk.
The TRM says, tbclk is derived from SYSCLKOUT. SYSCLKOUT is nothing but
ehrpwm functional clock derived from the gateable interface and
functional clock of PWMSS(l4_root_clk_div).
Refer AM57x TRM SPRUHZ6E[1], Janurary 2016, Table 29-4 and
Section 29.2.2.1, Table 29-19 and the NOTE at the end of the table.

[1] http://www.ti.com/lit/ug/spruhz6e/spruhz6e.pdf

Signed-off-by: Vignesh R <vigneshr@...com>
Signed-off-by: Franklin S Cooper Jr <fcooper@...com>
---
Version 5 changes:
None

Version v4 changes:
Updated link to latest documentation

 arch/arm/boot/dts/dra7xx-clocks.dtsi | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index 357bede..d0bae06 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -2146,4 +2146,28 @@
 		ti,bit-shift = <0>;
 		reg = <0x558>;
 	};
+
+       ehrpwm0_tbclk: ehrpwm0_tbclk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&l4_root_clk_div>;
+		ti,bit-shift = <20>;
+		reg = <0x0558>;
+	};
+
+	ehrpwm1_tbclk: ehrpwm1_tbclk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&l4_root_clk_div>;
+		ti,bit-shift = <21>;
+		reg = <0x0558>;
+	};
+
+	ehrpwm2_tbclk: ehrpwm2_tbclk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&l4_root_clk_div>;
+		ti,bit-shift = <22>;
+		reg = <0x0558>;
+	};
 };
-- 
2.7.0