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Date: Tue, 8 Mar 2016 15:58:03 +0100 From: Thomas Petazzoni <thomas.petazzoni@...e-electrons.com> To: Boris Brezillon <boris.brezillon@...e-electrons.com> Cc: David Woodhouse <dwmw2@...radead.org>, Brian Norris <computersforpeace@...il.com>, linux-mtd@...ts.infradead.org, Chen-Yu Tsai <wens@...e.org>, linux-kernel@...r.kernel.org, linux-sunxi@...glegroups.com, Maxime Ripard <maxime.ripard@...e-electrons.com>, linux-arm-kernel@...ts.infradead.org Subject: Re: [PATCH 02/16] mtd: nand: sunxi: fix clk rate calculation Boris, On Mon, 7 Mar 2016 17:18:19 +0100, Boris Brezillon wrote: > Unlike what is specified in the Allwinner datasheets, the NAND clock rate > is not equal to 2/T but 1/T. Fix the clock rate selection accordingly. > > Signed-off-by: Boris Brezillon <boris.brezillon@...e-electrons.com> > --- > drivers/mtd/nand/sunxi_nand.c | 8 +------- > 1 file changed, 1 insertion(+), 7 deletions(-) > > diff --git a/drivers/mtd/nand/sunxi_nand.c b/drivers/mtd/nand/sunxi_nand.c > index 4d01e65..ab66d8d 100644 > --- a/drivers/mtd/nand/sunxi_nand.c > +++ b/drivers/mtd/nand/sunxi_nand.c > @@ -1208,13 +1208,7 @@ static int sunxi_nand_chip_set_timings(struct sunxi_nand_chip *chip, > /* Convert min_clk_period from picoseconds to nanoseconds */ > min_clk_period = DIV_ROUND_UP(min_clk_period, 1000); > > - /* > - * Convert min_clk_period into a clk frequency, then get the > - * appropriate rate for the NAND controller IP given this formula > - * (specified in the datasheet): > - * nand clk_rate = 2 * min_clk_rate > - */ When some HW works in a way that is *NOT* the one specified in the datasheet, I think you should rather add *more* comments about this aspect, rather than removing existing comments. Thomas -- Thomas Petazzoni, CTO, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com
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