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Message-ID: <2242962.kh0Ty0L2C4@phil>
Date: Wed, 09 Mar 2016 02:12:31 +0100
From: Heiko Stuebner <heiko@...ech.de>
To: Xing Zheng <zhengxing@...k-chips.com>
Cc: linux-rockchip@...ts.infradead.org, huangtao@...k-chips.com,
jay.xu@...k-chips.com, elaine.zhang@...k-chips.com,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...eaurora.org>, linux-clk@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [RESEND PATCH v2 1/5] clk: rockchip: add more mux parameters for new pll sources
Am Dienstag, 1. März 2016, 18:14:31 schrieb Xing Zheng:
> Thers are only two parent PLLs that APLL and GPLL for core on the
> previous SoCs (RK3066/RK3188/RK3288/RK3368). Hence, we set fixed
> GPLL as alternate parent when core is switching freq.
>
> Since RK3399 big.LITTLE architecture, we need to select and adapt
> more PLLs (ALPLL/ABPLL/DPLL/GPLL) sources.
>
> Signed-off-by: Xing Zheng <zhengxing@...k-chips.com>
note to self: looks good to go
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