linux-kernel - Re: [PATCH] dma: sun4i: expose block size and wait cycle configuration to DMA users

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Message-ID: <20160311062607.GP11154@localhost>
Date:	Fri, 11 Mar 2016 11:56:07 +0530
From:	Vinod Koul <vinod.koul@...el.com>
To:	Boris Brezillon <boris.brezillon@...e-electrons.com>
Cc:	Maxime Ripard <maxime.ripard@...e-electrons.com>,
	Dan Williams <dan.j.williams@...el.com>,
	dmaengine@...r.kernel.org, Chen-Yu Tsai <wens@...e.org>,
	linux-sunxi@...glegroups.com,
	Emilio López <emilio@...pez.com.ar>,
	linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] dma: sun4i: expose block size and wait cycle
 configuration to DMA users

On Wed, Mar 09, 2016 at 12:06:27PM +0100, Boris Brezillon wrote:
> On Tue, 8 Mar 2016 08:25:47 +0530
> Vinod Koul <vinod.koul@...el.com> wrote:
> > 
> > Why does dmaengine need to wait? Can you explain that
> 
> I don't have an answer for that one, but when I set WAIT_CYCLES to 1
> for the NAND use case it does not work. So I guess it is somehow
> related to how the DRQ line is controlled on the device side...

Is the WAIT cycle different for different usages or same for all
usages/channels?

-- 
~Vinod