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Message-ID: <56E2D994.8090005@amd.com>
Date: Fri, 11 Mar 2016 15:43:32 +0100
From: Christian König <christian.koenig@....com>
To: Josh Poimboeuf <jpoimboe@...hat.com>,
Alexander Deucher <Alexander.Deucher@....com>
CC: <dri-devel@...ts.freedesktop.org>, <linux-kernel@...r.kernel.org>,
<fengguang.wu@...el.com>, Ingo Molnar <mingo@...nel.org>
Subject: Re: [PATCH v2 1/2] drm/radeon: refactor CIK tiling table
initialization
Am 11.03.2016 um 15:18 schrieb Josh Poimboeuf:
> Simplify the control flow of cik_tiling_mode_table_init() similar to how
> it was done in gfx_v7_0.c and gfx_v8_0.c.
>
> Signed-off-by: Josh Poimboeuf <jpoimboe@...hat.com>
I'm not so deep into the tilling config stuff, but briefly skimming over
it it clearly looks good to me.
Patch is Acked-by: Christian König <christian.koenig@....com>
Thanks for the help,
Christian.
> ---
> drivers/gpu/drm/radeon/cik.c | 1691 +++++++++++++++++-------------------------
> 1 file changed, 666 insertions(+), 1025 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
> index 0600140..1a92ce7 100644
> --- a/drivers/gpu/drm/radeon/cik.c
> +++ b/drivers/gpu/drm/radeon/cik.c
> @@ -2343,9 +2343,13 @@ out:
> */
> static void cik_tiling_mode_table_init(struct radeon_device *rdev)
> {
> - const u32 num_tile_mode_states = 32;
> - const u32 num_secondary_tile_mode_states = 16;
> - u32 reg_offset, gb_tile_moden, split_equal_to_row_size;
> + u32 *tile = rdev->config.cik.tile_mode_array;
> + u32 *macrotile = rdev->config.cik.macrotile_mode_array;
> + const u32 num_tile_mode_states =
> + ARRAY_SIZE(rdev->config.cik.tile_mode_array);
> + const u32 num_secondary_tile_mode_states =
> + ARRAY_SIZE(rdev->config.cik.macrotile_mode_array);
> + u32 reg_offset, split_equal_to_row_size;
> u32 num_pipe_configs;
> u32 num_rbs = rdev->config.cik.max_backends_per_se *
> rdev->config.cik.max_shader_engines;
> @@ -2367,1032 +2371,669 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
> if (num_pipe_configs > 8)
> num_pipe_configs = 16;
>
> - if (num_pipe_configs == 16) {
> - for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
> - switch (reg_offset) {
> - case 0:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
> - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
> - break;
> - case 1:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
> - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
> - break;
> - case 2:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
> - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
> - break;
> - case 3:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
> - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
> - break;
> - case 4:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
> - TILE_SPLIT(split_equal_to_row_size));
> - break;
> - case 5:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> - PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
> - break;
> - case 6:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
> - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
> - break;
> - case 7:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
> - TILE_SPLIT(split_equal_to_row_size));
> - break;
> - case 8:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
> - PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
> - break;
> - case 9:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> - PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
> - break;
> - case 10:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 11:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 12:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 13:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> - PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
> - break;
> - case 14:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 16:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 17:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 27:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> - PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
> - break;
> - case 28:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 29:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 30:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - default:
> - gb_tile_moden = 0;
> - break;
> - }
> - rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;
> - WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
> - }
> - for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
> - switch (reg_offset) {
> - case 0:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 1:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 2:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 3:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 4:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> - NUM_BANKS(ADDR_SURF_8_BANK));
> - break;
> - case 5:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> - NUM_BANKS(ADDR_SURF_4_BANK));
> - break;
> - case 6:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> - NUM_BANKS(ADDR_SURF_2_BANK));
> - break;
> - case 8:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 9:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 10:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 11:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> - NUM_BANKS(ADDR_SURF_8_BANK));
> - break;
> - case 12:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> - NUM_BANKS(ADDR_SURF_4_BANK));
> - break;
> - case 13:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> - NUM_BANKS(ADDR_SURF_2_BANK));
> - break;
> - case 14:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> - NUM_BANKS(ADDR_SURF_2_BANK));
> - break;
> - default:
> - gb_tile_moden = 0;
> - break;
> - }
> - rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden;
> - WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);
> - }
> - } else if (num_pipe_configs == 8) {
> - for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
> - switch (reg_offset) {
> - case 0:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
> - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
> - break;
> - case 1:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
> - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
> - break;
> - case 2:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
> - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
> - break;
> - case 3:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
> - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
> - break;
> - case 4:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
> - TILE_SPLIT(split_equal_to_row_size));
> - break;
> - case 5:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> - PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
> - break;
> - case 6:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
> - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
> - break;
> - case 7:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
> - TILE_SPLIT(split_equal_to_row_size));
> - break;
> - case 8:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
> - PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
> - break;
> - case 9:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> - PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
> - break;
> - case 10:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 11:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 12:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 13:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> - PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
> - break;
> - case 14:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 16:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 17:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 27:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> - PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
> - break;
> - case 28:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 29:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 30:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - default:
> - gb_tile_moden = 0;
> - break;
> - }
> - rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;
> - WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
> - }
> - for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
> - switch (reg_offset) {
> - case 0:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 1:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 2:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 3:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 4:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> - NUM_BANKS(ADDR_SURF_8_BANK));
> - break;
> - case 5:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> - NUM_BANKS(ADDR_SURF_4_BANK));
> - break;
> - case 6:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> - NUM_BANKS(ADDR_SURF_2_BANK));
> - break;
> - case 8:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 9:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 10:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 11:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 12:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> - NUM_BANKS(ADDR_SURF_8_BANK));
> - break;
> - case 13:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> - NUM_BANKS(ADDR_SURF_4_BANK));
> - break;
> - case 14:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> - NUM_BANKS(ADDR_SURF_2_BANK));
> - break;
> - default:
> - gb_tile_moden = 0;
> - break;
> - }
> - rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden;
> - WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);
> - }
> - } else if (num_pipe_configs == 4) {
> + for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
> + tile[reg_offset] = 0;
> + for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
> + macrotile[reg_offset] = 0;
> +
> + switch(num_pipe_configs) {
> + case 16:
> + tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
> + tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
> + tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
> + tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
> + tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
> + TILE_SPLIT(split_equal_to_row_size));
> + tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
> + tile[6] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
> + tile[7] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
> + TILE_SPLIT(split_equal_to_row_size));
> + tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
> + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
> + tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
> + tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
> + tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[17] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
> + tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[30] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> +
> + macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_8_BANK));
> + macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_4_BANK));
> + macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_2_BANK));
> + macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_8_BANK));
> + macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_4_BANK));
> + macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_2_BANK));
> + macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_2_BANK));
> +
> + for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
> + WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);
> + for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
> + WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]);
> + break;
> +
> + case 8:
> + tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
> + tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
> + tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
> + tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
> + tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
> + TILE_SPLIT(split_equal_to_row_size));
> + tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
> + tile[6] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
> + tile[7] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
> + TILE_SPLIT(split_equal_to_row_size));
> + tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
> + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
> + tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
> + tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
> + tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[17] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
> + tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[30] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> +
> + macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_8_BANK));
> + macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_4_BANK));
> + macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_2_BANK));
> + macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_8_BANK));
> + macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_4_BANK));
> + macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_2_BANK));
> +
> + for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
> + WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);
> + for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
> + WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]);
> + break;
> +
> + case 4:
> if (num_rbs == 4) {
> - for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
> - switch (reg_offset) {
> - case 0:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P4_16x16) |
> - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
> - break;
> - case 1:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P4_16x16) |
> - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
> - break;
> - case 2:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P4_16x16) |
> - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
> - break;
> - case 3:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P4_16x16) |
> - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
> - break;
> - case 4:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P4_16x16) |
> - TILE_SPLIT(split_equal_to_row_size));
> - break;
> - case 5:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> - PIPE_CONFIG(ADDR_SURF_P4_16x16) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
> - break;
> - case 6:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P4_16x16) |
> - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
> - break;
> - case 7:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P4_16x16) |
> - TILE_SPLIT(split_equal_to_row_size));
> - break;
> - case 8:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
> - PIPE_CONFIG(ADDR_SURF_P4_16x16));
> - break;
> - case 9:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> - PIPE_CONFIG(ADDR_SURF_P4_16x16) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
> - break;
> - case 10:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P4_16x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 11:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 12:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P4_16x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 13:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> - PIPE_CONFIG(ADDR_SURF_P4_16x16) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
> - break;
> - case 14:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P4_16x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 16:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 17:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P4_16x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 27:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> - PIPE_CONFIG(ADDR_SURF_P4_16x16) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
> - break;
> - case 28:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P4_16x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 29:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 30:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P4_16x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - default:
> - gb_tile_moden = 0;
> - break;
> - }
> - rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;
> - WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
> - }
> + tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P4_16x16) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
> + tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P4_16x16) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
> + tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P4_16x16) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
> + tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P4_16x16) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
> + tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P4_16x16) |
> + TILE_SPLIT(split_equal_to_row_size));
> + tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P4_16x16) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
> + tile[6] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P4_16x16) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
> + tile[7] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P4_16x16) |
> + TILE_SPLIT(split_equal_to_row_size));
> + tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
> + PIPE_CONFIG(ADDR_SURF_P4_16x16));
> + tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P4_16x16) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
> + tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P4_16x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P4_16x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P4_16x16) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
> + tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P4_16x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[17] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P4_16x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P4_16x16) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
> + tile[28] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P4_16x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[30] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P4_16x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> +
> } else if (num_rbs < 4) {
> - for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
> - switch (reg_offset) {
> - case 0:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
> - break;
> - case 1:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
> - break;
> - case 2:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
> - break;
> - case 3:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
> - break;
> - case 4:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> - TILE_SPLIT(split_equal_to_row_size));
> - break;
> - case 5:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> - PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
> - break;
> - case 6:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
> - break;
> - case 7:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> - TILE_SPLIT(split_equal_to_row_size));
> - break;
> - case 8:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
> - PIPE_CONFIG(ADDR_SURF_P4_8x16));
> - break;
> - case 9:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> - PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
> - break;
> - case 10:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 11:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 12:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 13:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> - PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
> - break;
> - case 14:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 16:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 17:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 27:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> - PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
> - break;
> - case 28:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 29:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 30:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - default:
> - gb_tile_moden = 0;
> - break;
> - }
> - rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;
> - WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
> - }
> - }
> - for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
> - switch (reg_offset) {
> - case 0:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 1:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 2:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 3:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 4:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 5:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> - NUM_BANKS(ADDR_SURF_8_BANK));
> - break;
> - case 6:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> - NUM_BANKS(ADDR_SURF_4_BANK));
> - break;
> - case 8:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 9:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 10:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 11:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 12:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 13:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> - NUM_BANKS(ADDR_SURF_8_BANK));
> - break;
> - case 14:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> - NUM_BANKS(ADDR_SURF_4_BANK));
> - break;
> - default:
> - gb_tile_moden = 0;
> - break;
> - }
> - rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden;
> - WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);
> - }
> - } else if (num_pipe_configs == 2) {
> - for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
> - switch (reg_offset) {
> - case 0:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P2) |
> - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
> - break;
> - case 1:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P2) |
> - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
> - break;
> - case 2:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P2) |
> - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
> - break;
> - case 3:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P2) |
> - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
> - break;
> - case 4:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P2) |
> - TILE_SPLIT(split_equal_to_row_size));
> - break;
> - case 5:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> - PIPE_CONFIG(ADDR_SURF_P2) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
> - break;
> - case 6:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P2) |
> - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
> - break;
> - case 7:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P2) |
> - TILE_SPLIT(split_equal_to_row_size));
> - break;
> - case 8:
> - gb_tile_moden = ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
> - PIPE_CONFIG(ADDR_SURF_P2);
> - break;
> - case 9:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P2));
> - break;
> - case 10:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P2) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 11:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P2) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 12:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P2) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 13:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> - PIPE_CONFIG(ADDR_SURF_P2) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
> - break;
> - case 14:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P2) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 16:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P2) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 17:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P2) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 27:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P2));
> - break;
> - case 28:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P2) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 29:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P2) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 30:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P2) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - default:
> - gb_tile_moden = 0;
> - break;
> - }
> - rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;
> - WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
> - }
> - for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
> - switch (reg_offset) {
> - case 0:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 1:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 2:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 3:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 4:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 5:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 6:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> - NUM_BANKS(ADDR_SURF_8_BANK));
> - break;
> - case 8:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 9:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 10:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 11:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 12:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 13:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 14:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> - NUM_BANKS(ADDR_SURF_8_BANK));
> - break;
> - default:
> - gb_tile_moden = 0;
> - break;
> - }
> - rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden;
> - WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);
> + tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
> + tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
> + tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
> + tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
> + tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + TILE_SPLIT(split_equal_to_row_size));
> + tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
> + tile[6] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
> + tile[7] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + TILE_SPLIT(split_equal_to_row_size));
> + tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16));
> + tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
> + tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
> + tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[17] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
> + tile[28] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[30] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> }
> - } else
> +
> + macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> + NUM_BANKS(ADDR_SURF_8_BANK));
> + macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_4_BANK));
> + macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> + NUM_BANKS(ADDR_SURF_8_BANK));
> + macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_4_BANK));
> +
> + for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
> + WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);
> + for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
> + WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]);
> + break;
> +
> + case 2:
> + tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P2) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
> + tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P2) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
> + tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P2) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
> + tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P2) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
> + tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P2) |
> + TILE_SPLIT(split_equal_to_row_size));
> + tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P2) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
> + tile[6] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P2) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
> + tile[7] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P2) |
> + TILE_SPLIT(split_equal_to_row_size));
> + tile[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
> + PIPE_CONFIG(ADDR_SURF_P2);
> + tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P2));
> + tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P2) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P2) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P2) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P2) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
> + tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P2) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P2) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[17] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P2) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P2));
> + tile[28] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P2) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P2) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[30] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P2) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> +
> + macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> + NUM_BANKS(ADDR_SURF_8_BANK));
> + macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> + NUM_BANKS(ADDR_SURF_8_BANK));
> +
> + for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
> + WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);
> + for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
> + WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]);
> + break;
> +
> + default:
> DRM_ERROR("unknown num pipe config: 0x%x\n", num_pipe_configs);
> + }
> }
>
> /**
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