linux-kernel - [PATCH v3 8/9] clk: rockchip: associate SCLK_MAC

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Message-Id: <1457942520-12859-9-git-send-email-wxt@rock-chips.com>
Date:	Mon, 14 Mar 2016 16:01:59 +0800
From:	Caesar Wang <wxt@...k-chips.com>
To:	Heiko Stuebner <heiko@...ech.de>,
	"David S. Miller" <davem@...emloft.net>,
	Rob Herring <robh+dt@...nel.org>
Cc:	linux-rockchip@...ts.infradead.org, keescook@...gle.com,
	leozwang@...gle.com, sergei.shtylyov@...entembedded.com,
	netdev@...r.kernel.org,
	Michael Turquette <mturquette@...libre.com>,
	Stephen Boyd <sboyd@...eaurora.org>, linux-clk@...r.kernel.org,
	Caesar Wang <wxt@...k-chips.com>,
	linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: [PATCH v3 8/9] clk: rockchip: associate SCLK_MAC_PLL and disable reparenting on rk3036

From: Heiko Stuebner <heiko@...ech.de>

The emac needs constant and very specific rate but the possible PLL-sources
are very limited, so we expect the PLL source to be set manually on per
board and don't want it to get changed in an automatic way later.
So add the necessary clock-id and disable reparenting on set_rate calls.

Signed-off-by: Heiko Stuebner <heiko@...ech.de>
Cc: Michael Turquette <mturquette@...libre.com>
Cc: Heiko Stuebner <heiko@...ech.de>
Cc: Stephen Boyd <sboyd@...eaurora.org>
Cc: linux-clk@...r.kernel.org

Signed-off-by: Caesar Wang <wxt@...k-chips.com>
---

Changes in v3:
- Add the Cc people.

Changes in v2: None

 drivers/clk/rockchip/clk-rk3036.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c
index cc66e5f..7cdb2d6 100644
--- a/drivers/clk/rockchip/clk-rk3036.c
+++ b/drivers/clk/rockchip/clk-rk3036.c
@@ -348,7 +348,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
 			RK2928_CLKSEL_CON(16), 0, 2, MFLAGS, 2, 5, DFLAGS,
 			RK2928_CLKGATE_CON(10), 5, GFLAGS),
 
-	COMPOSITE_NOGATE(0, "mac_pll_src", mux_pll_src_3plls_p, 0,
+	COMPOSITE_NOGATE(SCLK_MACPLL, "mac_pll_src", mux_pll_src_3plls_p, CLK_SET_RATE_NO_REPARENT,
 			RK2928_CLKSEL_CON(21), 0, 2, MFLAGS, 9, 5, DFLAGS),
 	MUX(SCLK_MACREF, "mac_clk_ref", mux_mac_p, CLK_SET_RATE_PARENT,
 			RK2928_CLKSEL_CON(21), 3, 1, MFLAGS),
-- 
1.9.1